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[188.155.168.84]) by smtp.gmail.com with ESMTPSA id bf21sm14968026edb.2.2022.01.29.11.36.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Jan 2022 11:36:49 -0800 (PST) From: Krzysztof Kozlowski To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Guenter Roeck , Marek Szyprowski , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 1/8] arm64: dts: exynos: adjust USB DRD clocks with dtschema in Exynos7 Date: Sat, 29 Jan 2022 20:36:39 +0100 Message-Id: <20220129193646.372481-1-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220129_113714_100481_F14F0CC8 X-CRM114-Status: GOOD ( 11.33 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Use the same order of USB 3.0 DRD controller clocks as in Exynos5433. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 3364b09c3158..e38bb02a2152 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -684,11 +684,10 @@ usbdrd_phy: phy@15500000 { reg = <0x15500000 0x100>; clocks = <&clock_fsys0 ACLK_USBDRD300>, <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, - <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, + <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, <&clock_fsys0 SCLK_USBDRD300_REFCLK>; - clock-names = "phy", "ref", "phy_pipe", - "phy_utmi", "itp"; + clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <1>; };