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X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Describe the SerDes block #1 using the generic phys infrastructure. This way, the ethernet nodes can each reference their serdes lanes individually using the 'phys' dts property. Signed-off-by: Ioana Ciornei --- Changes in v2: - none .../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 ++ .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 41 +++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi index 17f8e733972a..14a6334adff2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi @@ -63,21 +63,25 @@ sfp3: sfp-3 { &dpmac7 { sfp = <&sfp0>; managed = "in-band-status"; + phys = <&serdes1_lane_d>; }; &dpmac8 { sfp = <&sfp1>; managed = "in-band-status"; + phys = <&serdes1_lane_c>; }; &dpmac9 { sfp = <&sfp2>; managed = "in-band-status"; + phys = <&serdes1_lane_b>; }; &dpmac10 { sfp = <&sfp3>; managed = "in-band-status"; + phys = <&serdes1_lane_a>; }; &emdio2 { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 7032505f5ef3..04f29c086512 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -612,6 +612,47 @@ soc { ranges; dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; + serdes_1: serdes_phy@1ea0000 { + compatible = "fsl,lynx-28g"; + reg = <0x00 0x1ea0000 0x0 0x1e30>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + + serdes1_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + serdes1_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + serdes1_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + serdes1_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + serdes1_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + serdes1_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + serdes1_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + serdes1_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; + }; + crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; fsl,sec-era = <10>;