[v2] phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED

Commit Message

Marek Vasut April 13, 2022, 2:07 p.m. UTC

The 'fsl,refclk-pad-mode' DT property used to select clock source for
PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT,
IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first
two options are handled correctly by the driver, the last one is not,
this patch implements support for the last option.

The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input,
the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC
internal PLL and output to PCIE_RESREF external IO pin. The last
IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY
clock are sourced from SoC internal PLL and not output anywhere.

Reviewed-by: Richard Zhu <[e-mail]>
Signed-off-by: Marek Vasut <[e-mail]>
Cc: Fabio Estevam <[e-mail]>
Cc: Kishon Vijay Abraham I <[e-mail]>
Cc: Marcel Ziswiler <[e-mail]>
Cc: NXP Linux Team <[e-mail]>
Cc: Peng Fan <[e-mail]>
Cc: Richard Zhu <[e-mail]>
Cc: Shawn Guo <[e-mail]>
Cc: Vinod Koul <[e-mail]>
Cc: [e-mail]
To: [e-mail]
---
V2: Rebase on phy/next
---
 drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Comments

Vinod Koul April 20, 2022, 9:16 a.m. UTC | #1

On 13-04-22, 16:07, Marek Vasut wrote:
> The 'fsl,refclk-pad-mode' DT property used to select clock source for
> PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT,
> IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first
> two options are handled correctly by the driver, the last one is not,
> this patch implements support for the last option.
> 
> The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input,
> the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC
> internal PLL and output to PCIE_RESREF external IO pin. The last
> IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY
> clock are sourced from SoC internal PLL and not output anywhere.

Applied, thanks

Patch

diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index f1eb03ba25d61..ad7d2edfc4146 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -94,15 +94,21 @@  static int imx8_pcie_phy_init(struct phy *phy)
 			   IMX8MM_GPR_PCIE_CMN_RST);
 	usleep_range(200, 500);
 
-	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) {
+	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
+	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
 		/* Configure the pad as input */
 		val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
 		writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
-	} else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) {
+	} else {
 		/* Configure the PHY to output the refclock via pad */
 		writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
+	}
+
+	if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT ||
+	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
+		/* Source clock from SoC internal PLL */
 		writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,
 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
 		writel(AUX_PLL_REFCLK_SEL_SYS_PLL,