| Message ID | 20220419010852.452169-2-victor.liu@nxp.com |
|---|---|
| State | Accepted |
| Commit | 69ed3dd6be9cf5d75252940b9a927dff4bab7860 |
| Headers | show |
| Series | phy: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support | expand |
On Tue, 19 Apr 2022 at 03:07, Liu Ying <victor.liu@nxp.com> wrote: > > The Northwest Logic MIPI DSI host controller embedded in i.MX8qxp > works with a Mixel MIPI DPHY + LVDS PHY combo to support either > a MIPI DSI display or a LVDS display. So, this patch calls > phy_set_mode() from nwl_dsi_mode_set() to set PHY mode to MIPI DPHY > explicitly. > > Cc: Guido Günther <agx@sigxcpu.org> > Cc: Robert Chiras <robert.chiras@nxp.com> > Cc: Martin Kepplinger <martin.kepplinger@puri.sm> > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > Cc: Neil Armstrong <narmstrong@baylibre.com> > Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> > Cc: Jonas Karlman <jonas@kwiboo.se> > Cc: Jernej Skrabec <jernej.skrabec@gmail.com> > Cc: David Airlie <airlied@linux.ie> > Cc: Daniel Vetter <daniel@ffwll.ch> > Cc: NXP Linux Team <linux-imx@nxp.com> > Signed-off-by: Liu Ying <victor.liu@nxp.com> > --- > v7->v8: > * Resend with Andrzej's and Jernej's mail addressed updated. > > v6->v7: > * No change. > > v5->v6: > * Rebase the series upon v5.17-rc1. > * Set PHY mode in ->mode_set() instead of ->pre_enable() in the nwl-dsi > bridge driver due to the rebase. > * Drop Guido's R-b tag due to the rebase. > > v4->v5: > * No change. > > v3->v4: > * No change. > > v2->v3: > * No change. > > v1->v2: > * Add Guido's R-b tag. > > drivers/gpu/drm/bridge/nwl-dsi.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c > index d5945501a5ee..85bab7372af1 100644 > --- a/drivers/gpu/drm/bridge/nwl-dsi.c > +++ b/drivers/gpu/drm/bridge/nwl-dsi.c > @@ -666,6 +666,12 @@ static int nwl_dsi_mode_set(struct nwl_dsi *dsi) > return ret; > } > > + ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); > + if (ret < 0) { > + DRM_DEV_ERROR(dev, "Failed to set DSI phy mode: %d\n", ret); > + goto uninit_phy; > + } > + > ret = phy_configure(dsi->phy, phy_cfg); > if (ret < 0) { > DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret); > -- > 2.25.1 > Acked-by: Robert Foss <robert.foss@linaro.org>
Hi, On Tue, Apr 19, 2022 at 09:08:48AM +0800, Liu Ying wrote: > The Northwest Logic MIPI DSI host controller embedded in i.MX8qxp > works with a Mixel MIPI DPHY + LVDS PHY combo to support either > a MIPI DSI display or a LVDS display. So, this patch calls > phy_set_mode() from nwl_dsi_mode_set() to set PHY mode to MIPI DPHY > explicitly. > > Cc: Guido Günther <agx@sigxcpu.org> > Cc: Robert Chiras <robert.chiras@nxp.com> > Cc: Martin Kepplinger <martin.kepplinger@puri.sm> > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > Cc: Neil Armstrong <narmstrong@baylibre.com> > Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> > Cc: Jonas Karlman <jonas@kwiboo.se> > Cc: Jernej Skrabec <jernej.skrabec@gmail.com> > Cc: David Airlie <airlied@linux.ie> > Cc: Daniel Vetter <daniel@ffwll.ch> > Cc: NXP Linux Team <linux-imx@nxp.com> > Signed-off-by: Liu Ying <victor.liu@nxp.com> > --- > v7->v8: > * Resend with Andrzej's and Jernej's mail addressed updated. > > v6->v7: > * No change. > > v5->v6: > * Rebase the series upon v5.17-rc1. > * Set PHY mode in ->mode_set() instead of ->pre_enable() in the nwl-dsi > bridge driver due to the rebase. > * Drop Guido's R-b tag due to the rebase. > > v4->v5: > * No change. > > v3->v4: > * No change. > > v2->v3: > * No change. > > v1->v2: > * Add Guido's R-b tag. > > drivers/gpu/drm/bridge/nwl-dsi.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c > index d5945501a5ee..85bab7372af1 100644 > --- a/drivers/gpu/drm/bridge/nwl-dsi.c > +++ b/drivers/gpu/drm/bridge/nwl-dsi.c > @@ -666,6 +666,12 @@ static int nwl_dsi_mode_set(struct nwl_dsi *dsi) > return ret; > } > > + ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); > + if (ret < 0) { > + DRM_DEV_ERROR(dev, "Failed to set DSI phy mode: %d\n", ret); > + goto uninit_phy; > + } > + > ret = phy_configure(dsi->phy, phy_cfg); > if (ret < 0) { > DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", > ret); I can't currently test this but it still looks good so Reviewed-by: Guido Günther <agx@sigxcpu.org> Cheers, -- Guido > -- > 2.25.1 >
Hi, On Fri, 2022-04-22 at 19:24 +0200, Guido Günther wrote: > Hi, > On Tue, Apr 19, 2022 at 09:08:48AM +0800, Liu Ying wrote: > > The Northwest Logic MIPI DSI host controller embedded in i.MX8qxp > > works with a Mixel MIPI DPHY + LVDS PHY combo to support either > > a MIPI DSI display or a LVDS display. So, this patch calls > > phy_set_mode() from nwl_dsi_mode_set() to set PHY mode to MIPI DPHY > > explicitly. > > > > Cc: Guido Günther <agx@sigxcpu.org> > > Cc: Robert Chiras <robert.chiras@nxp.com> > > Cc: Martin Kepplinger <martin.kepplinger@puri.sm> > > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > > Cc: Neil Armstrong <narmstrong@baylibre.com> > > Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> > > Cc: Jonas Karlman <jonas@kwiboo.se> > > Cc: Jernej Skrabec <jernej.skrabec@gmail.com> > > Cc: David Airlie <airlied@linux.ie> > > Cc: Daniel Vetter <daniel@ffwll.ch> > > Cc: NXP Linux Team <linux-imx@nxp.com> > > Signed-off-by: Liu Ying <victor.liu@nxp.com> Hope this patch won't fall through the cracks. Can someone please apply it to drm-misc-next? Robert? Thanks, Liu Ying > > --- > > v7->v8: > > * Resend with Andrzej's and Jernej's mail addressed updated. > > > > v6->v7: > > * No change. > > > > v5->v6: > > * Rebase the series upon v5.17-rc1. > > * Set PHY mode in ->mode_set() instead of ->pre_enable() in the > > nwl-dsi > > bridge driver due to the rebase. > > * Drop Guido's R-b tag due to the rebase. > > > > v4->v5: > > * No change. > > > > v3->v4: > > * No change. > > > > v2->v3: > > * No change. > > > > v1->v2: > > * Add Guido's R-b tag. > > > > drivers/gpu/drm/bridge/nwl-dsi.c | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c > > b/drivers/gpu/drm/bridge/nwl-dsi.c > > index d5945501a5ee..85bab7372af1 100644 > > --- a/drivers/gpu/drm/bridge/nwl-dsi.c > > +++ b/drivers/gpu/drm/bridge/nwl-dsi.c > > @@ -666,6 +666,12 @@ static int nwl_dsi_mode_set(struct nwl_dsi > > *dsi) > > return ret; > > } > > > > + ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); > > + if (ret < 0) { > > + DRM_DEV_ERROR(dev, "Failed to set DSI phy mode: %d\n", > > ret); > > + goto uninit_phy; > > + } > > + > > ret = phy_configure(dsi->phy, phy_cfg); > > if (ret < 0) { > > DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", > > ret); > > I can't currently test this but it still looks good so > > Reviewed-by: Guido Günther <agx@sigxcpu.org> > > Cheers, > -- Guido > > > -- > > 2.25.1 > >
Hi Liu, On Fri, Apr 29, 2022 at 08:30:43PM +0800, Liu Ying wrote: > Hi, > > On Fri, 2022-04-22 at 19:24 +0200, Guido Günther wrote: > > Hi, > > On Tue, Apr 19, 2022 at 09:08:48AM +0800, Liu Ying wrote: > > > The Northwest Logic MIPI DSI host controller embedded in i.MX8qxp > > > works with a Mixel MIPI DPHY + LVDS PHY combo to support either > > > a MIPI DSI display or a LVDS display. So, this patch calls > > > phy_set_mode() from nwl_dsi_mode_set() to set PHY mode to MIPI DPHY > > > explicitly. > > > > > > Cc: Guido Günther <agx@sigxcpu.org> > > > Cc: Robert Chiras <robert.chiras@nxp.com> > > > Cc: Martin Kepplinger <martin.kepplinger@puri.sm> > > > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > > > Cc: Neil Armstrong <narmstrong@baylibre.com> > > > Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> > > > Cc: Jonas Karlman <jonas@kwiboo.se> > > > Cc: Jernej Skrabec <jernej.skrabec@gmail.com> > > > Cc: David Airlie <airlied@linux.ie> > > > Cc: Daniel Vetter <daniel@ffwll.ch> > > > Cc: NXP Linux Team <linux-imx@nxp.com> > > > Signed-off-by: Liu Ying <victor.liu@nxp.com> > > Hope this patch won't fall through the cracks. > Can someone please apply it to drm-misc-next? Robert? Applied to drm-misc-next. Cheers, -- Guido > > Thanks, > Liu Ying > > > > --- > > > v7->v8: > > > * Resend with Andrzej's and Jernej's mail addressed updated. > > > > > > v6->v7: > > > * No change. > > > > > > v5->v6: > > > * Rebase the series upon v5.17-rc1. > > > * Set PHY mode in ->mode_set() instead of ->pre_enable() in the > > > nwl-dsi > > > bridge driver due to the rebase. > > > * Drop Guido's R-b tag due to the rebase. > > > > > > v4->v5: > > > * No change. > > > > > > v3->v4: > > > * No change. > > > > > > v2->v3: > > > * No change. > > > > > > v1->v2: > > > * Add Guido's R-b tag. > > > > > > drivers/gpu/drm/bridge/nwl-dsi.c | 6 ++++++ > > > 1 file changed, 6 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c > > > b/drivers/gpu/drm/bridge/nwl-dsi.c > > > index d5945501a5ee..85bab7372af1 100644 > > > --- a/drivers/gpu/drm/bridge/nwl-dsi.c > > > +++ b/drivers/gpu/drm/bridge/nwl-dsi.c > > > @@ -666,6 +666,12 @@ static int nwl_dsi_mode_set(struct nwl_dsi > > > *dsi) > > > return ret; > > > } > > > > > > + ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); > > > + if (ret < 0) { > > > + DRM_DEV_ERROR(dev, "Failed to set DSI phy mode: %d\n", > > > ret); > > > + goto uninit_phy; > > > + } > > > + > > > ret = phy_configure(dsi->phy, phy_cfg); > > > if (ret < 0) { > > > DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", > > > ret); > > > > I can't currently test this but it still looks good so > > > > Reviewed-by: Guido Günther <agx@sigxcpu.org> > > > > Cheers, > > -- Guido > > > > > -- > > > 2.25.1 > > > >
diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c index d5945501a5ee..85bab7372af1 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -666,6 +666,12 @@ static int nwl_dsi_mode_set(struct nwl_dsi *dsi) return ret; } + ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); + if (ret < 0) { + DRM_DEV_ERROR(dev, "Failed to set DSI phy mode: %d\n", ret); + goto uninit_phy; + } + ret = phy_configure(dsi->phy, phy_cfg); if (ret < 0) { DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret);
The Northwest Logic MIPI DSI host controller embedded in i.MX8qxp works with a Mixel MIPI DPHY + LVDS PHY combo to support either a MIPI DSI display or a LVDS display. So, this patch calls phy_set_mode() from nwl_dsi_mode_set() to set PHY mode to MIPI DPHY explicitly. Cc: Guido Günther <agx@sigxcpu.org> Cc: Robert Chiras <robert.chiras@nxp.com> Cc: Martin Kepplinger <martin.kepplinger@puri.sm> Cc: Andrzej Hajda <andrzej.hajda@intel.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> Cc: Jonas Karlman <jonas@kwiboo.se> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: NXP Linux Team <linux-imx@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> --- v7->v8: * Resend with Andrzej's and Jernej's mail addressed updated. v6->v7: * No change. v5->v6: * Rebase the series upon v5.17-rc1. * Set PHY mode in ->mode_set() instead of ->pre_enable() in the nwl-dsi bridge driver due to the rebase. * Drop Guido's R-b tag due to the rebase. v4->v5: * No change. v3->v4: * No change. v2->v3: * No change. v1->v2: * Add Guido's R-b tag. drivers/gpu/drm/bridge/nwl-dsi.c | 6 ++++++ 1 file changed, 6 insertions(+)