From patchwork Tue Apr 26 13:21:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 12827163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01F69C433EF for ; Tue, 26 Apr 2022 13:23:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1nezodSAwEmQ7GfROLvDKn2qql88sGtU88ve3zqC4dU=; b=d1yiPCx8862m8H cCyBD250FBYOceZzYrhkIFL16ytmlPjRNaD9d1Df3+jXhybtTrD2HNpBm4hzNm0kytrqlzaTRQynN 4sxdCNfRk6A30TJFHeWVVdSd4LgGRrn4L/yyGvF3NtMxrvAzosjLeMD8J4jmK3woDEfYbMxYqUGzp NsaY6wBJdhlwPVqCPXt2Dn8zHtz/pmqZG8f/Jd9vae0+nFjS4Htlq3AYor+Iz6FOs8EyiuFqCatNh 6s7GJrwSvcbFGrH8umyyg0LGi23OrNXY3WDWqpyMxyjRnVnP7qRTKjiGYhs6EDZE8i/ZXCdZpPncJ MVtrHrQlVJxnoenYFzZA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njL9q-00EYU6-7d; Tue, 26 Apr 2022 13:23:10 +0000 Received: from mxout4.routing.net ([2a03:2900:1:a::9]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1njL8k-00EXkR-35; Tue, 26 Apr 2022 13:22:05 +0000 Received: from mxbox1.masterlogin.de (unknown [192.168.10.88]) by mxout4.routing.net (Postfix) with ESMTP id DBA271009A7; Tue, 26 Apr 2022 13:21:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1650979316; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/I3vczkANniTDx1yzkb6F3Q+qN8yNcM3KZAsi+3HfMw=; b=RKnCSZXRQ7fnjTXzbdlcvkOK6K98elSoFn72BifrXeGGDcl2cP+e/pEX/NiynIrEb2Temo 9s7uAx3ZLpWWkiX3Dz6hwIhY7dv8U74Mej3F5DI9qtQIu2hAzRaKRc2qW2M1Lf+i3d4Gjv +r+l+8L0uiYdZsonvmi2nE5iJfVxooU= Received: from localhost.localdomain (fttx-pool-80.245.77.37.bambit.de [80.245.77.37]) by mxbox1.masterlogin.de (Postfix) with ESMTPSA id DFCC74059D; Tue, 26 Apr 2022 13:21:54 +0000 (UTC) From: Frank Wunderlich To: linux-rockchip@lists.infradead.org Cc: Frank Wunderlich , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Kishon Vijay Abraham I , Vinod Koul , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Philipp Zabel , Johan Jonker , Peter Geis , Michael Riesch , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [RFC/RFT v2 01/11] dt-bindings: phy: rockchip: add PCIe v3 phy Date: Tue, 26 Apr 2022 15:21:29 +0200 Message-Id: <20220426132139.26761-2-linux@fw-web.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220426132139.26761-1-linux@fw-web.de> References: <20220426132139.26761-1-linux@fw-web.de> MIME-Version: 1.0 X-Mail-ID: 32b2cd93-5553-4018-86a3-43385b6d0de2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220426_062202_350438_87BF7AA1 X-CRM114-Status: GOOD ( 13.94 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: Frank Wunderlich Add a new binding file for Rockchip PCIe v3 phy driver. Signed-off-by: Frank Wunderlich --- v2: dt-bindings: rename yaml for PCIe v3 rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml changes in pcie3 phy yaml - change clock names to ordered const list - extend pcie30-phymode description - add phy-cells to required properties - drop unevaluatedProperties - example with 1 clock each line - use default property instead of text describing it - update license --- .../bindings/phy/rockchip,pcie3-phy.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml new file mode 100644 index 000000000000..3592888b5ee2 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PCIe v3 phy + +maintainers: + - Heiko Stuebner + +properties: + compatible: + enum: + - rockchip,rk3568-pcie3-phy + - rockchip,rk3588-pcie3-phy + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + items: + - const: "refclk_m" + - const: "refclk_n" + - const: "pclk" + + minItems: 1 + + "#phy-cells": + const: 0 + + resets: + maxItems: 1 + + reset-names: + const: phy + + rockchip,phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the phy "general register files" + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the pipe "general register files" + + rockchip,pcie30-phymode: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + set the phy-mode for enabling bifurcation + bit0: bifurcation for port 0 + bit1: bifurcation for port 1 + bit2: aggregation + constants are defined in the dt-bindings/phy/phy-rockchip-pcie3.h + minimum: 0x0 + maximum: 0x4 + default: 0x4 + +required: + - compatible + - reg + - rockchip,phy-grf + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, + <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + };