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[1/2] dt-bindings: phy: Add Freescale i.MX8qm Mixel LVDS PHY binding

Message ID 20220618092201.3837791-2-victor.liu@nxp.com
State Superseded
Headers show
Series phy: freescale: Add i.MX8qm Mixel LVDS PHY support | expand

Commit Message

Liu Ying June 18, 2022, 9:22 a.m. UTC 
This patch adds bindings for Mixel LVDS PHY found on
Freescale i.MX8qm SoC.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
 .../bindings/phy/mixel,lvds-phy.yaml          | 64 +++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml

Comments

Krzysztof Kozlowski June 19, 2022, 12:11 p.m. UTC | #1 
On 18/06/2022 11:22, Liu Ying wrote:
> This patch adds bindings for Mixel LVDS PHY found on
> Freescale i.MX8qm SoC.
> 
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
>  .../bindings/phy/mixel,lvds-phy.yaml          | 64 +++++++++++++++++++
>  1 file changed, 64 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
> new file mode 100644
> index 000000000000..de964ffb9356
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
> @@ -0,0 +1,64 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mixel,lvds-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mixel LVDS PHY for Freescale i.MX8qm SoC

If Mixel is a vendor, it needs it's vendor prefix documented and used in
compatible. Filename should match compatible. If it is not a vendor,
then filename should be "fsl,imx8qm-lvds-phy.yaml"

> +
> +maintainers:
> +  - Liu Ying <victor.liu@nxp.com>
> +
> +description: |
> +  The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
> +  It converts two groups of four 7/10 bits of CMOS data into two
> +  groups of four data lanes of LVDS data streams. A phase-locked
> +  transmit clock is transmitted in parallel with each group of
> +  data streams over a fifth LVDS link. Every cycle of the transmit
> +  clock, 56/80 bits of input data are sampled and transmitted
> +  through the two groups of LVDS data streams. Together with the
> +  transmit clocks, the two groups of LVDS data streams form two
> +  LVDS channels.
> +
> +  The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
> +  by Control and Status Registers(CSR) module in the SoC. The CSR
> +  module, as a system controller, contains the PHY's registers.
> +
> +properties:
> +  compatible:
> +    const: fsl,imx8qm-lvds-phy
> +
> +  "#phy-cells":
> +    const: 1
> +    description: |
> +      Cell allows setting the LVDS channel index of the PHY.
> +      Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    const: phy_ref

Maybe just skip the clock-names, it's not bringing anything useful,
unless you expect some more clocks to be documented later? (but in such
case question would be why they are not documented now)

> +
> +  power-domains:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - "#phy-cells"
> +  - clocks
> +  - clock-names
> +  - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/firmware/imx/rsrc.h>
> +    phy {
> +        compatible = "fsl,imx8qm-lvds-phy";
> +        #phy-cells = <1>;
> +        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
> +        clock-names = "phy_ref";
> +        power-domains = <&pd IMX_SC_R_LVDS_0>;
> +    };


Best regards,
Krzysztof
Liu Ying June 20, 2022, 3:06 a.m. UTC | #2 
On Sun, 2022-06-19 at 14:11 +0200, Krzysztof Kozlowski wrote:
> On 18/06/2022 11:22, Liu Ying wrote:
> > This patch adds bindings for Mixel LVDS PHY found on
> > Freescale i.MX8qm SoC.
> > 
> > Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > ---
> >  .../bindings/phy/mixel,lvds-phy.yaml          | 64
> > +++++++++++++++++++
> >  1 file changed, 64 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-
> > phy.yaml b/Documentation/devicetree/bindings/phy/mixel,lvds-
> > phy.yaml
> > new file mode 100644
> > index 000000000000..de964ffb9356
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
> > @@ -0,0 +1,64 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: 
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fphy%2Fmixel%2Clvds-phy.yaml%23&amp;data=05%7C01%7Cvictor.liu%40nxp.com%7Cb68f9012ddcc44bc10cd08da51ece7f7%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637912375188731290%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=MdBILPYmfYeWeCXXNxy1mu1NcU0b6EW3QztYc294dd4%3D&amp;reserved=0
> > +$schema: 
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=05%7C01%7Cvictor.liu%40nxp.com%7Cb68f9012ddcc44bc10cd08da51ece7f7%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637912375188731290%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=MhHwku8rbDLAZAQh1T9CGFULMkk5MaNoj3LQnQJ6VXM%3D&amp;reserved=0
> > +
> > +title: Mixel LVDS PHY for Freescale i.MX8qm SoC
> 
> If Mixel is a vendor, it needs it's vendor prefix documented and used
> in
> compatible. Filename should match compatible. If it is not a vendor,
> then filename should be "fsl,imx8qm-lvds-phy.yaml"

Mixel is a vendor. I'll document the vendor prefix and set
'fsl,imx8qm-lvds-phy' and 'mixel,lvds-phy' as compatible's enum.
I'll keep the filename as-is.

> 
> > +
> > +maintainers:
> > +  - Liu Ying <victor.liu@nxp.com>
> > +
> > +description: |
> > +  The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
> > +  It converts two groups of four 7/10 bits of CMOS data into two
> > +  groups of four data lanes of LVDS data streams. A phase-locked
> > +  transmit clock is transmitted in parallel with each group of
> > +  data streams over a fifth LVDS link. Every cycle of the transmit
> > +  clock, 56/80 bits of input data are sampled and transmitted
> > +  through the two groups of LVDS data streams. Together with the
> > +  transmit clocks, the two groups of LVDS data streams form two
> > +  LVDS channels.
> > +
> > +  The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
> > +  by Control and Status Registers(CSR) module in the SoC. The CSR
> > +  module, as a system controller, contains the PHY's registers.
> > +
> > +properties:
> > +  compatible:
> > +    const: fsl,imx8qm-lvds-phy
> > +
> > +  "#phy-cells":
> > +    const: 1
> > +    description: |
> > +      Cell allows setting the LVDS channel index of the PHY.
> > +      Index 0 is for LVDS channel0 and index 1 is for LVDS
> > channel1.
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  clock-names:
> > +    const: phy_ref
> 
> Maybe just skip the clock-names, it's not bringing anything useful,
> unless you expect some more clocks to be documented later? (but in
> such
> case question would be why they are not documented now)

I'll skip it, because it is the only clock required by the PHY IP that
I'm aware of.

Thanks,
Liu Ying

> 
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - "#phy-cells"
> > +  - clocks
> > +  - clock-names
> > +  - power-domains
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/firmware/imx/rsrc.h>
> > +    phy {
> > +        compatible = "fsl,imx8qm-lvds-phy";
> > +        #phy-cells = <1>;
> > +        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
> > +        clock-names = "phy_ref";
> > +        power-domains = <&pd IMX_SC_R_LVDS_0>;
> > +    };
> 
> 
> Best regards,
> Krzysztof
Krzysztof Kozlowski June 20, 2022, 7:35 a.m. UTC | #3 
On 20/06/2022 05:06, Liu Ying wrote:
> On Sun, 2022-06-19 at 14:11 +0200, Krzysztof Kozlowski wrote:
>> On 18/06/2022 11:22, Liu Ying wrote:
>>> This patch adds bindings for Mixel LVDS PHY found on
>>> Freescale i.MX8qm SoC.
>>>
>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>> ---
>>>  .../bindings/phy/mixel,lvds-phy.yaml          | 64
>>> +++++++++++++++++++
>>>  1 file changed, 64 insertions(+)
>>>  create mode 100644
>>> Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
>>
>>> diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-
>>> phy.yaml b/Documentation/devicetree/bindings/phy/mixel,lvds-
>>> phy.yaml
>>> new file mode 100644
>>> index 000000000000..de964ffb9356
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
>>> @@ -0,0 +1,64 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: 
>>> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fphy%2Fmixel%2Clvds-phy.yaml%23&amp;data=05%7C01%7Cvictor.liu%40nxp.com%7Cb68f9012ddcc44bc10cd08da51ece7f7%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637912375188731290%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=MdBILPYmfYeWeCXXNxy1mu1NcU0b6EW3QztYc294dd4%3D&amp;reserved=0
>>> +$schema: 
>>> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=05%7C01%7Cvictor.liu%40nxp.com%7Cb68f9012ddcc44bc10cd08da51ece7f7%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637912375188731290%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=MhHwku8rbDLAZAQh1T9CGFULMkk5MaNoj3LQnQJ6VXM%3D&amp;reserved=0
>>> +
>>> +title: Mixel LVDS PHY for Freescale i.MX8qm SoC
>>
>> If Mixel is a vendor, it needs it's vendor prefix documented and used
>> in
>> compatible. Filename should match compatible. If it is not a vendor,
>> then filename should be "fsl,imx8qm-lvds-phy.yaml"
> 
> Mixel is a vendor. I'll document the vendor prefix and set
> 'fsl,imx8qm-lvds-phy' and 'mixel,lvds-phy' as compatible's enum.
> I'll keep the filename as-is.
mixel,lvds-phy is not a good compatible (and filename) because it is not
specific about component version. Please use specific compatibles only
thus also specific filename (filename should match first compatible).

Best regards,
Krzysztof
Liu Ying June 20, 2022, 7:56 a.m. UTC | #4 
On Mon, 2022-06-20 at 09:35 +0200, Krzysztof Kozlowski wrote:
> On 20/06/2022 05:06, Liu Ying wrote:
> > On Sun, 2022-06-19 at 14:11 +0200, Krzysztof Kozlowski wrote:
> > > On 18/06/2022 11:22, Liu Ying wrote:
> > > > This patch adds bindings for Mixel LVDS PHY found on
> > > > Freescale i.MX8qm SoC.
> > > > 
> > > > Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > > > ---
> > > >  .../bindings/phy/mixel,lvds-phy.yaml          | 64
> > > > +++++++++++++++++++
> > > >  1 file changed, 64 insertions(+)
> > > >  create mode 100644
> > > > Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
> > > > diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-
> > > > phy.yaml b/Documentation/devicetree/bindings/phy/mixel,lvds-
> > > > phy.yaml
> > > > new file mode 100644
> > > > index 000000000000..de964ffb9356
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
> > > > @@ -0,0 +1,64 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: 
> > > > 
https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fphy%2Fmixel%2Clvds-phy.yaml%23&amp;data=05%7C01%7Cvictor.liu%40nxp.com%7Cc7d6216ac12148ec95d008da528f78eb%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637913073407696040%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=m588CiXOaJhWFbpEal3MjZaHtvOTUOVIujydIdPxSHg%3D&amp;reserved=0
> > > > +$schema: 
> > > > 
https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=05%7C01%7Cvictor.liu%40nxp.com%7Cc7d6216ac12148ec95d008da528f78eb%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637913073407696040%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=IGn5f05QrzyX05k%2FKgTitdq6OYN2FmdpsO6qHXun55Y%3D&amp;reserved=0
> > > > +
> > > > +title: Mixel LVDS PHY for Freescale i.MX8qm SoC
> > > 
> > > If Mixel is a vendor, it needs it's vendor prefix documented and
> > > used
> > > in
> > > compatible. Filename should match compatible. If it is not a
> > > vendor,
> > > then filename should be "fsl,imx8qm-lvds-phy.yaml"
> > 
> > Mixel is a vendor. I'll document the vendor prefix and set
> > 'fsl,imx8qm-lvds-phy' and 'mixel,lvds-phy' as compatible's enum.
> > I'll keep the filename as-is.
> 
> mixel,lvds-phy is not a good compatible (and filename) because it is
> not
> specific about component version. Please use specific compatibles
> only
> thus also specific filename (filename should match first compatible).

All the information about component version I can find in the PHY IP's
data sheet is '28FDSOI-LVDS-1250-8CH-TX-PLL'. '28FDSOI' looks like the
technology name. Do you think the compatible name can be
'mixel,lvds-1250-8ch-tx-pll'? Or, any better option?

If the compatible name is ok, does the below compabitle property look
ok?

===================8<==============
  compatible:
    enum:
      - mixel,lvds-1250-8ch-tx-pll
      - fsl,imx8qm-lvds-phy
===================8<==============

I'll change the filename accordingly.

Thanks,
Liu Ying
Krzysztof Kozlowski June 20, 2022, 10:38 a.m. UTC | #5 
On 20/06/2022 09:56, Liu Ying wrote:
> On Mon, 2022-06-20 at 09:35 +0200, Krzysztof Kozlowski wrote:
>> On 20/06/2022 05:06, Liu Ying wrote:
>>> On Sun, 2022-06-19 at 14:11 +0200, Krzysztof Kozlowski wrote:
>>>> On 18/06/2022 11:22, Liu Ying wrote:
>>>>> This patch adds bindings for Mixel LVDS PHY found on
>>>>> Freescale i.MX8qm SoC.
>>>>>
>>>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>>>> ---
>>>>>  .../bindings/phy/mixel,lvds-phy.yaml          | 64
>>>>> +++++++++++++++++++
>>>>>  1 file changed, 64 insertions(+)
>>>>>  create mode 100644
>>>>> Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
>>>>> diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-
>>>>> phy.yaml b/Documentation/devicetree/bindings/phy/mixel,lvds-
>>>>> phy.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..de964ffb9356
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
>>>>> @@ -0,0 +1,64 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: 
>>>>>
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fphy%2Fmixel%2Clvds-phy.yaml%23&amp;data=05%7C01%7Cvictor.liu%40nxp.com%7Cc7d6216ac12148ec95d008da528f78eb%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637913073407696040%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=m588CiXOaJhWFbpEal3MjZaHtvOTUOVIujydIdPxSHg%3D&amp;reserved=0
>>>>> +$schema: 
>>>>>
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=05%7C01%7Cvictor.liu%40nxp.com%7Cc7d6216ac12148ec95d008da528f78eb%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637913073407696040%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=IGn5f05QrzyX05k%2FKgTitdq6OYN2FmdpsO6qHXun55Y%3D&amp;reserved=0
>>>>> +
>>>>> +title: Mixel LVDS PHY for Freescale i.MX8qm SoC
>>>>
>>>> If Mixel is a vendor, it needs it's vendor prefix documented and
>>>> used
>>>> in
>>>> compatible. Filename should match compatible. If it is not a
>>>> vendor,
>>>> then filename should be "fsl,imx8qm-lvds-phy.yaml"
>>>
>>> Mixel is a vendor. I'll document the vendor prefix and set
>>> 'fsl,imx8qm-lvds-phy' and 'mixel,lvds-phy' as compatible's enum.
>>> I'll keep the filename as-is.
>>
>> mixel,lvds-phy is not a good compatible (and filename) because it is
>> not
>> specific about component version. Please use specific compatibles
>> only
>> thus also specific filename (filename should match first compatible).
> 
> All the information about component version I can find in the PHY IP's
> data sheet is '28FDSOI-LVDS-1250-8CH-TX-PLL'. '28FDSOI' looks like the
> technology name. Do you think the compatible name can be
> 'mixel,lvds-1250-8ch-tx-pll'? Or, any better option?
> 
> If the compatible name is ok, does the below compabitle property look
> ok?
> 
> ===================8<==============
>   compatible:
>     enum:
>       - mixel,lvds-1250-8ch-tx-pll
>       - fsl,imx8qm-lvds-phy
> ===================8<==============

https://mixel.com/wp-content/mixel/pdf/2018/MXL-LVDS-1250-8CH-TX-PLL_SS_28FDSOI.pdf

mentions entire name as a device name, so with 28FDSOI, but your choice
is also good.


Best regards,
Krzysztof
Liu Ying June 20, 2022, 12:08 p.m. UTC | #6 
On Mon, 2022-06-20 at 12:38 +0200, Krzysztof Kozlowski wrote:
> On 20/06/2022 09:56, Liu Ying wrote:
> > On Mon, 2022-06-20 at 09:35 +0200, Krzysztof Kozlowski wrote:
> > > On 20/06/2022 05:06, Liu Ying wrote:
> > > > On Sun, 2022-06-19 at 14:11 +0200, Krzysztof Kozlowski wrote:
> > > > > On 18/06/2022 11:22, Liu Ying wrote:
> > > > > > This patch adds bindings for Mixel LVDS PHY found on
> > > > > > Freescale i.MX8qm SoC.
> > > > > > 
> > > > > > Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > > > > > ---
> > > > > >  .../bindings/phy/mixel,lvds-phy.yaml          | 64
> > > > > > +++++++++++++++++++
> > > > > >  1 file changed, 64 insertions(+)
> > > > > >  create mode 100644
> > > > > > Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
> > > > > > diff --git
> > > > > > a/Documentation/devicetree/bindings/phy/mixel,lvds-
> > > > > > phy.yaml
> > > > > > b/Documentation/devicetree/bindings/phy/mixel,lvds-
> > > > > > phy.yaml
> > > > > > new file mode 100644
> > > > > > index 000000000000..de964ffb9356
> > > > > > --- /dev/null
> > > > > > +++ b/Documentation/devicetree/bindings/phy/mixel,lvds-
> > > > > > phy.yaml
> > > > > > @@ -0,0 +1,64 @@
> > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > +%YAML 1.2
> > > > > > +---
> > > > > > +$id: 
> > > > > > 
> > 
> > 
https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fphy%2Fmixel%2Clvds-phy.yaml%23&amp;data=05%7C01%7Cvictor.liu%40nxp.com%7C968d5a1e2f5c4ccdd77908da52a9148d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637913183390683087%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=h8JmjvGBnTcMn2Uk3CVgq%2BB4%2BlbCBA5iDD7OhtFZyZo%3D&amp;reserved=0
> > > > > > +$schema: 
> > > > > > 
> > 
> > 
https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=05%7C01%7Cvictor.liu%40nxp.com%7C968d5a1e2f5c4ccdd77908da52a9148d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637913183390683087%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=bLsmtGPC8tzZSHPqblHOhx0gnsgFHlKVu0P8dN6G15s%3D&amp;reserved=0
> > > > > > +
> > > > > > +title: Mixel LVDS PHY for Freescale i.MX8qm SoC
> > > > > 
> > > > > If Mixel is a vendor, it needs it's vendor prefix documented
> > > > > and
> > > > > used
> > > > > in
> > > > > compatible. Filename should match compatible. If it is not a
> > > > > vendor,
> > > > > then filename should be "fsl,imx8qm-lvds-phy.yaml"
> > > > 
> > > > Mixel is a vendor. I'll document the vendor prefix and set
> > > > 'fsl,imx8qm-lvds-phy' and 'mixel,lvds-phy' as compatible's
> > > > enum.
> > > > I'll keep the filename as-is.
> > > 
> > > mixel,lvds-phy is not a good compatible (and filename) because it
> > > is
> > > not
> > > specific about component version. Please use specific compatibles
> > > only
> > > thus also specific filename (filename should match first
> > > compatible).
> > 
> > All the information about component version I can find in the PHY
> > IP's
> > data sheet is '28FDSOI-LVDS-1250-8CH-TX-PLL'. '28FDSOI' looks like
> > the
> > technology name. Do you think the compatible name can be
> > 'mixel,lvds-1250-8ch-tx-pll'? Or, any better option?
> > 
> > If the compatible name is ok, does the below compabitle property
> > look
> > ok?
> > 
> > ===================8<==============
> >   compatible:
> >     enum:
> >       - mixel,lvds-1250-8ch-tx-pll
> >       - fsl,imx8qm-lvds-phy
> > ===================8<==============
> 
> 
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fmixel.com%2Fwp-content%2Fmixel%2Fpdf%2F2018%2FMXL-LVDS-1250-8CH-TX-PLL_SS_28FDSOI.pdf&amp;data=05%7C01%7Cvictor.liu%40nxp.com%7C968d5a1e2f5c4ccdd77908da52a9148d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637913183390683087%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=PWK82Pf%2FbBti6PXNq9wvFbjM6QmnZWcj7bWSh2FYAzA%3D&amp;reserved=0
> 
> mentions entire name as a device name, so with 28FDSOI, but your
> choice
> is also good.

Will use the entire name with 28FDSOI.

Thanks,
Liu Ying
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
new file mode 100644
index 000000000000..de964ffb9356
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
@@ -0,0 +1,64 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mixel,lvds-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mixel LVDS PHY for Freescale i.MX8qm SoC
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+description: |
+  The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
+  It converts two groups of four 7/10 bits of CMOS data into two
+  groups of four data lanes of LVDS data streams. A phase-locked
+  transmit clock is transmitted in parallel with each group of
+  data streams over a fifth LVDS link. Every cycle of the transmit
+  clock, 56/80 bits of input data are sampled and transmitted
+  through the two groups of LVDS data streams. Together with the
+  transmit clocks, the two groups of LVDS data streams form two
+  LVDS channels.
+
+  The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
+  by Control and Status Registers(CSR) module in the SoC. The CSR
+  module, as a system controller, contains the PHY's registers.
+
+properties:
+  compatible:
+    const: fsl,imx8qm-lvds-phy
+
+  "#phy-cells":
+    const: 1
+    description: |
+      Cell allows setting the LVDS channel index of the PHY.
+      Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: phy_ref
+
+  power-domains:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#phy-cells"
+  - clocks
+  - clock-names
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/firmware/imx/rsrc.h>
+    phy {
+        compatible = "fsl,imx8qm-lvds-phy";
+        #phy-cells = <1>;
+        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
+        clock-names = "phy_ref";
+        power-domains = <&pd IMX_SC_R_LVDS_0>;
+    };