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[95.114.61.215]) by smtp.googlemail.com with ESMTPSA id f13-20020a170906824d00b00726e108b566sm622871ejx.173.2022.06.28.05.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 05:45:22 -0700 (PDT) From: Martin Blumenstingl To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com, Martin Blumenstingl Subject: [PATCH v1 7/9] reset: intel: Use syscon_node_to_regmap on legacy SoCs Date: Tue, 28 Jun 2022 14:44:39 +0200 Message-Id: <20220628124441.2385023-8-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> References: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220628_054528_037368_99F2623B X-CRM114-Status: GOOD ( 16.40 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Older Lantiq (called "legacy") SoCs the RCU registers have more than just the reset controller registers. It additionally contains boot media selection information, up to two USB2 PHYs and configuration for various other peripherals (such as the PCIe PHY). use syscon_node_to_regmap() to obtain the regmap on these SoCs. Signed-off-by: Martin Blumenstingl --- drivers/reset/Kconfig | 3 ++- drivers/reset/reset-intel-gw.c | 29 +++++++++++++++++++---------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 68a5ea44612e..fb49c465078f 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -86,7 +86,8 @@ config RESET_INTEL_GW bool "Intel Reset Controller Driver" depends on X86 || LANTIQ || COMPILE_TEST depends on OF && HAS_IOMEM - select REGMAP_MMIO + select REGMAP_MMIO if X86 + select MFD_SYSCON if LANTIQ help This enables the reset controller driver for Intel Gateway SoCs. Say Y to control the reset signals provided by reset controller. diff --git a/drivers/reset/reset-intel-gw.c b/drivers/reset/reset-intel-gw.c index 46ed7a693666..0bf7fe4e77ae 100644 --- a/drivers/reset/reset-intel-gw.c +++ b/drivers/reset/reset-intel-gw.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -170,7 +171,6 @@ static int intel_reset_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; struct intel_reset_data *data; - void __iomem *base; u32 rb_id[3]; int ret; @@ -182,15 +182,24 @@ static int intel_reset_probe(struct platform_device *pdev) if (!data->soc_data) return -ENODEV; - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - data->regmap = devm_regmap_init_mmio(dev, base, - &intel_rcu_regmap_config); - if (IS_ERR(data->regmap)) { - dev_err(dev, "regmap initialization failed\n"); - return PTR_ERR(data->regmap); + if (data->soc_data->legacy) { + data->regmap = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(data->regmap)) + return dev_err_probe(dev, PTR_ERR(data->regmap), + "Failed to get regmap from syscon node\n"); + } else { + void __iomem *base; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + data->regmap = devm_regmap_init_mmio(dev, base, + &intel_rcu_regmap_config); + if (IS_ERR(data->regmap)) { + dev_err(dev, "regmap initialization failed\n"); + return PTR_ERR(data->regmap); + } } ret = device_property_read_u32_array(dev, "intel,global-reset", rb_id,