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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qOULPihdtXQs/jZXUiFTkESyv2VdRFK+68at8ktgUKWX3UbNtq1sjpqeVIxtNH/51ydU6TyEdWQXj1m7Kt2tARrmDZmedi5Ptntj0ps45MYY1T6eHJ9+m/FtgZG5sePHwhlDEDJixfucLNwp0tGurkcW9lbMmJWlky6IL5rCPWLvQ9YIe9p0LNHUlgnGVplS60PFRWMF5ylbWG1KAtbtIGNuKRd9IqJKb/qca7WEN/NUDh9JgVZFMjC7gfsbvQUaNCNDNJwVFvECU35irlUHpOujw4suENUVkw18gx4rVodIQg2tfN3HZi1ZB0dWXFjGulclg6faQkTyOWljkZUP6ZE2oN3nYltiHkSH8AKPDXymOr7Hnig0lgldYA7yI+36cB6fA47bccflN3osYoRbugWyTBQ2rNr2BoK9h8lu87p5unvb3UcAAd/s0uliBaPv6BFTkWLDA3Slm4SqB+g0F8DQToS2YYuiim8uppf0fDEPnCLU3Yo2sU8/8OkMOIdw89M5jq/dJnBDh13yF2z93iYY2ec6hwcHcLDOsPECInKHeY8uhT0sAkaixbozyhBsmTMaghsgyj7P5jcECt9UAk3UnpN7QaHmNUIy8rG2hcvaUa8Hxd58uuS5UJ8eftJWjzSHzPiS38n9fL0d/CsDVK7NrJM9jaEiZr2x1KB3kD/ySfGLNgiX7UNiCb3AJ50aRlxNytrawouADmnKdjq4W8sLV/BAaLN1+MWFT3kR5sC+NV8sSWk5tmdpA48NhuKQuBSuXGNvfCNrbeZTIFlGePqIV13xXud6J6QoZYftYj/uTIiEyItrni3I/R7EWrENXks0taDAFVfHKmpi+UNlxhPvGbnL1psPWGgwmOpf8oW8FaBoULxGmu70Ef0ObEkflM8wBU9S0QyMjOELFmPAvEw0hq9qL9xoFviGGWuXMZdNnQZJuwGUVCym1/Tq8NJNAnJifnN1dxzDlCHNWE0HiusFGDJCbXxQjZQjkI2hpoIxVmv6Ep6EoAVYc6Os7oDnQz2qzVpjG6MnO4TUQx6DasuNlZJ3/thfEHgMeH67QUiRlnDlUGPdUBfG3EKcMxgeURrCov3UdwonRkOMfrU1p+aKqEdeWD0srjE00kpzT+hmE2kHYUYJt37SCdwJ3xl3upIDmlBnnHqYCvBadxnepD2NNvjecqO35EUlF4YPi8rAtWL7+baSxs56brIwEwaKMlgBUnCgkSkA5h9VIFFSV9jir+UgokkdY/o2ro4V2BhCrWGseLAhntOJAaY5A9YbXkItDb0mtQ3tgn4kBrv3u0ELFbds5tia3y/q+UbQE2CHkfz6UyEf8nipdp0MueImZL5hGigUYCtmtOZQxf91gqrounv7UWo8YSB5WMKExqAZyoG9KF05wjsmT22BI6cHnHzokrdfVw5vSukKm9U/gOAVkAisCptRaFLgIasR6Q4GURrgLVup4v7U4ilNEi3/fxjwe8rbuqpFCvwut791SLKSbCwy4IXZzahorTC290wf0kUCSWXiL2+HRaHWR7Bhv+MReuKLvi6XqPs/8hgrODaBKzfac1VajZa5S/zVf0YMvF6lXV8ydS4gl7epxtNdpORpQ8/ZSQ2rnopUnQ2RxA== X-OriginatorOrg: seco.com X-MS-Exchange-CrossTenant-Network-Message-Id: b566126f-5ff3-4c60-f736-08da76659438 X-MS-Exchange-CrossTenant-AuthSource: DB7PR03MB4972.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2022 22:06:27.8288 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: EOPewZsdbCNxVldkjs49hgCvPNegaoHwqofL6Lc0J4S96A+YJcbUG5KZy1bKwLhzoc5Y80Wlge8qiXeVzuRq9Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB8419 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220804_150639_958676_C0F90E2F X-CRM114-Status: GOOD ( 12.97 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This is a first stab at adding serdes support on the LS1088A. Linux hangs around when the serdes is initialized if the si5341 is enabled, so it's commented out. The MC firmware needs to be fairly new (it must support DPAA2_MAC_FEATURE_PROTOCOL_CHANGE), and the DPC needs to set the macs to MAC_LINK_TYPE_BACKPLANE. For this reason, I think this will be difficult to do in a backwards-compatible manner. I have not really tested this, but hopefully it can be a good starting point. Signed-off-by: Sean Anderson --- Changes in v4: - Convert to new bindings .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 161 ++++++++++++++++++ 1 file changed, 161 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 1bfbce69cc8b..7279d914843c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -10,17 +10,138 @@ /dts-v1/; +#include + #include "fsl-ls1088a.dtsi" / { model = "LS1088A RDB Board"; compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; + + clocks { + si5341_xtal: clock-48mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + clk_100mhz: clock-100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk_156mhz: clock-156mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + }; + + ovdd: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "ovdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + dvdd: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "dvdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + +}; + +&serdes1 { + //clocks = <&si5341 0 8>, <&si5341 0 9>; + clocks = <&clk_100mhz>, <&clk_156mhz>; + clock-names = "ref0", "ref1"; + status = "okay"; + + serdes1_0: phy@0 { + #phy-cells = <0>; + reg = <0>; + + /* SG2 */ + sgmii-3 { + fsl,pccr = <0x8>; + fsl,index = <3>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* XFI2 */ + xfi-1 { + fsl,pccr = <0xb>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_1: phy@1 { + #phy-cells = <0>; + reg = <1>; + + /* SG1 */ + sgmii-2 { + fsl,pccr = <0x8>; + fsl,index = <2>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* + * XFI2 + * Table 23-1 and section 23.5.16.4 disagree; this reflects the + * table. + */ + xfi-0 { + fsl,pccr = <0xb>; + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_2: phy@2 { + #phy-cells = <0>; + reg = <2>; + + /* QSGb */ + qsgmii-1 { + fsl,pccr = <0x9>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_3: phy@2 { + #phy-cells = <0>; + reg = <2>; + + /* QSGa */ + qsgmii-0 { + fsl,pccr = <0x9>; + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; +}; + +&dpmac1 { + phys = <&serdes1_1>; }; &dpmac2 { phy-handle = <&mdio2_aquantia_phy>; phy-connection-type = "10gbase-r"; pcs-handle = <&pcs2>; + phys = <&serdes1_0>; }; &dpmac3 { @@ -28,6 +149,7 @@ &dpmac3 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_0>; + phys = <&serdes1_3>; }; &dpmac4 { @@ -35,6 +157,7 @@ &dpmac4 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_1>; + phys = <&serdes1_3>; }; &dpmac5 { @@ -42,6 +165,7 @@ &dpmac5 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_2>; + phys = <&serdes1_3>; }; &dpmac6 { @@ -49,6 +173,7 @@ &dpmac6 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_3>; + phys = <&serdes1_3>; }; &dpmac7 { @@ -56,6 +181,7 @@ &dpmac7 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_0>; + phys = <&serdes1_2>; }; &dpmac8 { @@ -63,6 +189,7 @@ &dpmac8 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_1>; + phys = <&serdes1_2>; }; &dpmac9 { @@ -70,6 +197,7 @@ &dpmac9 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_2>; + phys = <&serdes1_2>; }; &dpmac10 { @@ -77,6 +205,7 @@ &dpmac10 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_3>; + phys = <&serdes1_2>; }; &emdio1 { @@ -142,6 +271,38 @@ i2c-switch@77 { #address-cells = <1>; #size-cells = <0>; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + si5341: clock-generator@74 { + #address-cells = <1>; + #clock-cells = <2>; + #size-cells = <0>; + compatible = "silabs,si5341"; + reg = <0x74>; + clocks = <&si5341_xtal>; + clock-names = "xtal"; + vdd-supply = <&ovdd>; + vdda-supply = <&dvdd>; + vddo8-supply = <&ovdd>; + vddo9-supply = <&ovdd>; + silabs,iovdd-33; + status = "disabled"; + + out@8 { + reg = <8>; + silabs,format = <1>; + }; + + out@9 { + reg = <9>; + silabs,format = <1>; + }; + }; + }; + i2c@2 { #address-cells = <1>; #size-cells = <0>;