| Message ID | 20220919-v1-2-4844816c9808@baylibre.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add MT8195 HDMI support | expand |
On Tue, Sep 20, 2022 at 12:59 AM Guillaume Ranquet <granquet@baylibre.com> wrote: > > From: Pablo Sun <pablo.sun@mediatek.com> > > Add the clock gate definition for the DPI1 hardware > in VDOSYS1. > > The parent clock "hdmi_txpll" is already defined in > `mt8195.dtsi`. > > Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
On Mon, Sep 26, 2022 at 1:09 PM Chen-Yu Tsai <wenst@chromium.org> wrote: > > On Tue, Sep 20, 2022 at 12:59 AM Guillaume Ranquet > <granquet@baylibre.com> wrote: > > > > From: Pablo Sun <pablo.sun@mediatek.com> > > > > Add the clock gate definition for the DPI1 hardware > > in VDOSYS1. > > > > The parent clock "hdmi_txpll" is already defined in > > `mt8195.dtsi`. > > > > Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> I've queued patches 1 & 2 up here [1] and will send a pull request to the clock maintainer later this week. [1] https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux.git/log/?h=clk-mtk-for-6.1
diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c index d54d7726d186..835335b9d87b 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -34,6 +34,12 @@ static const struct mtk_gate_regs vdo1_3_cg_regs = { .sta_ofs = 0x140, }; +static const struct mtk_gate_regs vdo1_4_cg_regs = { + .set_ofs = 0x400, + .clr_ofs = 0x400, + .sta_ofs = 0x400, +}; + #define GATE_VDO1_0(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) @@ -50,6 +56,9 @@ static const struct mtk_gate_regs vdo1_3_cg_regs = { #define GATE_VDO1_3(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define GATE_VDO1_4(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + static const struct mtk_gate vdo1_clks[] = { /* VDO1_0 */ GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0), @@ -107,6 +116,8 @@ static const struct mtk_gate vdo1_clks[] = { GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf", "top_vpp", 17), /* VDO1_3 */ GATE_VDO1_3(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8), + /* VDO1_4 */ + GATE_VDO1_4(CLK_VDO1_DPI1_HDMI, "vdo1_dpi1_hdmi", "hdmi_txpll", 0), }; static int clk_mt8195_vdo1_probe(struct platform_device *pdev)