| Message ID | 20221011131416.2478-10-johan+linaro@kernel.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | phy: qcom-qmp: further prep cleanups | expand |
On 11/10/2022 16:14, Johan Hovold wrote: > The power-down delay was included in the first version of the QMP driver > for MSM8996 as an optional delay after powering on the PHY (using > POWER_DOWN_CONTROL) and just before starting it. Later changes modified > this sequence by powering on before initialising the PHY, but the > optional delay stayed where it was (i.e. before starting the PHY). > > The vendor driver does not use a delay before starting the PHY and this > is likely not needed on any platform unless there is a corresponding > delay in the vendor kernel init sequence tables (i.e. in devicetree). > > Let's keep the delay for now, but drop the redundant configuration > options while increasing the unnecessarily low timer slack somewhat. > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Note: the comment from the previous patch applies here too. > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 15 ++------------- > 1 file changed, 2 insertions(+), 13 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c > index 31ac405d3785..899be7bd4d92 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c > @@ -41,7 +41,7 @@ > > #define PHY_INIT_COMPLETE_TIMEOUT 10000 > #define POWER_DOWN_DELAY_US_MIN 10 > -#define POWER_DOWN_DELAY_US_MAX 11 > +#define POWER_DOWN_DELAY_US_MAX 20 > > struct qmp_phy_init_tbl { > unsigned int offset; > @@ -203,12 +203,6 @@ struct qmp_phy_cfg { > unsigned int mask_com_pcs_ready; > /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ > unsigned int phy_status; > - > - /* true, if PHY needs delay after POWER_DOWN */ > - bool has_pwrdn_delay; > - /* power_down delay in usec */ > - int pwrdn_delay_min; > - int pwrdn_delay_max; > }; > > /** > @@ -326,10 +320,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > .mask_com_pcs_ready = PCS_READY, > .phy_status = PHYSTATUS, > - > - .has_pwrdn_delay = true, > - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, > - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, > }; > > static void qmp_pcie_msm8996_configure_lane(void __iomem *base, > @@ -523,8 +513,7 @@ static int qmp_pcie_msm8996_power_on(struct phy *phy) > */ > qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); > > - if (cfg->has_pwrdn_delay) > - usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); > + usleep_range(POWER_DOWN_DELAY_US_MIN, POWER_DOWN_DELAY_US_MAX); > > /* Pull PHY out of reset state */ > qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 31ac405d3785..899be7bd4d92 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -41,7 +41,7 @@ #define PHY_INIT_COMPLETE_TIMEOUT 10000 #define POWER_DOWN_DELAY_US_MIN 10 -#define POWER_DOWN_DELAY_US_MAX 11 +#define POWER_DOWN_DELAY_US_MAX 20 struct qmp_phy_init_tbl { unsigned int offset; @@ -203,12 +203,6 @@ struct qmp_phy_cfg { unsigned int mask_com_pcs_ready; /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ unsigned int phy_status; - - /* true, if PHY needs delay after POWER_DOWN */ - bool has_pwrdn_delay; - /* power_down delay in usec */ - int pwrdn_delay_min; - int pwrdn_delay_max; }; /** @@ -326,10 +320,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .mask_com_pcs_ready = PCS_READY, .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, }; static void qmp_pcie_msm8996_configure_lane(void __iomem *base, @@ -523,8 +513,7 @@ static int qmp_pcie_msm8996_power_on(struct phy *phy) */ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); - if (cfg->has_pwrdn_delay) - usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); + usleep_range(POWER_DOWN_DELAY_US_MIN, POWER_DOWN_DELAY_US_MAX); /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
The power-down delay was included in the first version of the QMP driver for MSM8996 as an optional delay after powering on the PHY (using POWER_DOWN_CONTROL) and just before starting it. Later changes modified this sequence by powering on before initialising the PHY, but the optional delay stayed where it was (i.e. before starting the PHY). The vendor driver does not use a delay before starting the PHY and this is likely not needed on any platform unless there is a corresponding delay in the vendor kernel init sequence tables (i.e. in devicetree). Let's keep the delay for now, but drop the redundant configuration options while increasing the unnecessarily low timer slack somewhat. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-)