| Message ID | 20221012055602.1544944-3-uwu@icenowy.me |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | SUNIV USB and PopStick support (and updating mailmap) | expand |
On Wed, 12 Oct 2022 13:55:54 +0800 Icenowy Zheng <uwu@icenowy.me> wrote: > Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs, > because it has only one OTG USB controller, no host-only OHCI/EHCI > controllers. > > Add a binding document for it. Following the current situation of one > YAML file per SoC, this one is based on > allwinner,sun8i-v3s-usb-phy.yaml, but with OHCI/EHCI-related bits > removed. (The same driver in Linux, phy-sun4i-usb, covers all these > binding files now.) > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > Changes in v2: > - Clarify the relation with other phy-sun4i-usb bindings. > - Added Rob's ACK. > > .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++ > 1 file changed, 83 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml > new file mode 100644 > index 000000000000..22ff8e0f2331 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml > @@ -0,0 +1,83 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Allwinner F1C100s USB PHY Device Tree Bindings I see that commit dd3cb467ebb56 [1] discourages the redundant "Device Tree Bindings" suffix in the title name, so I think you should remove that. The rest looks alright to me, compared against the manual and what the driver expects, so with that fixed: Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cheers, Andre [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=dd3cb467ebb56 > + > +maintainers: > + - Chen-Yu Tsai <wens@csie.org> > + - Maxime Ripard <mripard@kernel.org> > + > +properties: > + "#phy-cells": > + const: 1 > + > + compatible: > + const: allwinner,suniv-f1c100s-usb-phy > + > + reg: > + maxItems: 1 > + description: PHY Control registers > + > + reg-names: > + const: phy_ctrl > + > + clocks: > + maxItems: 1 > + description: USB OTG PHY bus clock > + > + clock-names: > + const: usb0_phy > + > + resets: > + maxItems: 1 > + description: USB OTG reset > + > + reset-names: > + const: usb0_reset > + > + usb0_id_det-gpios: > + maxItems: 1 > + description: GPIO to the USB OTG ID pin > + > + usb0_vbus_det-gpios: > + maxItems: 1 > + description: GPIO to the USB OTG VBUS detect pin > + > + usb0_vbus_power-supply: > + description: Power supply to detect the USB OTG VBUS > + > + usb0_vbus-supply: > + description: Regulator controlling USB OTG VBUS > + > +required: > + - "#phy-cells" > + - compatible > + - clocks > + - clock-names > + - reg > + - reg-names > + - resets > + - reset-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/gpio/gpio.h> > + #include <dt-bindings/clock/suniv-ccu-f1c100s.h> > + #include <dt-bindings/reset/suniv-ccu-f1c100s.h> > + > + phy@1c13400 { > + compatible = "allwinner,suniv-f1c100s-usb-phy"; > + reg = <0x01c13400 0x10>; > + reg-names = "phy_ctrl"; > + clocks = <&ccu CLK_USB_PHY0>; > + clock-names = "usb0_phy"; > + resets = <&ccu RST_USB_PHY0>; > + reset-names = "usb0_reset"; > + #phy-cells = <1>; > + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; > + };
diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml new file mode 100644 index 000000000000..22ff8e0f2331 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner F1C100s USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + const: allwinner,suniv-f1c100s-usb-phy + + reg: + maxItems: 1 + description: PHY Control registers + + reg-names: + const: phy_ctrl + + clocks: + maxItems: 1 + description: USB OTG PHY bus clock + + clock-names: + const: usb0_phy + + resets: + maxItems: 1 + description: USB OTG reset + + reset-names: + const: usb0_reset + + usb0_id_det-gpios: + maxItems: 1 + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + maxItems: 1 + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/suniv-ccu-f1c100s.h> + #include <dt-bindings/reset/suniv-ccu-f1c100s.h> + + phy@1c13400 { + compatible = "allwinner,suniv-f1c100s-usb-phy"; + reg = <0x01c13400 0x10>; + reg-names = "phy_ctrl"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb0_phy"; + resets = <&ccu RST_USB_PHY0>; + reset-names = "usb0_reset"; + #phy-cells = <1>; + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; + };