| Message ID | 20221018084333.149790-2-s-vadapalli@ti.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support to PHY GMII SEL for J721e CPSW9G QSGMII | expand |
On Tue, 18 Oct 2022 14:13:31 +0530, Siddharth Vadapalli wrote: > TI's J721e SoC supports additional PHY modes like QSGMII and SGMII > that are not supported on earlier SoCs. Add a compatible for it. > > Extend ti,qsgmii-main-ports property to support selection of upto > two main ports at once across the two QSGMII interfaces. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > .../bindings/phy/ti,phy-gmii-sel.yaml | 48 +++++++++++++++---- > 1 file changed, 40 insertions(+), 8 deletions(-) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml:75:12: [error] syntax error: mapping values are not allowed here (syntax) dtschema/dtc warnings/errors: make[1]: *** Deleting file 'Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.example.dts' Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml:75:12: mapping values are not allowed in this context make[1]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.example.dts] Error 1 make[1]: *** Waiting for unfinished jobs.... ./Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml:75:12: mapping values are not allowed in this context ./Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml: ignoring, error parsing file make: *** [Makefile:1492: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
Hello Rob, On 18/10/22 19:02, Rob Herring wrote: > On Tue, 18 Oct 2022 14:13:31 +0530, Siddharth Vadapalli wrote: >> TI's J721e SoC supports additional PHY modes like QSGMII and SGMII >> that are not supported on earlier SoCs. Add a compatible for it. >> >> Extend ti,qsgmii-main-ports property to support selection of upto >> two main ports at once across the two QSGMII interfaces. >> >> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> >> --- >> .../bindings/phy/ti,phy-gmii-sel.yaml | 48 +++++++++++++++---- >> 1 file changed, 40 insertions(+), 8 deletions(-) >> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > ./Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml:75:12: [error] syntax error: mapping values are not allowed here (syntax) I will fix the errors in the v3 series and ensure that there are no errors or warnings with dt_binding_check, using the updated dt-schema and yamllint. Regards, Siddharth.
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml index da7cac537e15..afe210cde307 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml @@ -54,6 +54,7 @@ properties: - ti,dm814-phy-gmii-sel - ti,am654-phy-gmii-sel - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel reg: maxItems: 1 @@ -63,14 +64,17 @@ properties: ti,qsgmii-main-ports: $ref: /schemas/types.yaml#/definitions/uint32-array description: | - Required only for QSGMII mode. Array to select the port for - QSGMII main mode. Rest of the ports are selected as QSGMII_SUB - ports automatically. Any one of the 4 CPSW5G ports can act as the - main port with the rest of them being the QSGMII_SUB ports. - maxItems: 1 - items: - minimum: 1 - maximum: 4 + Required only for QSGMII mode. Array to select the port/s for QSGMII + main mode. The size of the array corresponds to the number of QSGMII + interfaces and thus, the number of distinct QSGMII main ports, + supported by the device. If the device supports two QSGMII interfaces + but only one QSGMII interface is desired, repeat the QSGMII main port + value corresponding to the QSGMII interface in the array. + minItems: 1 + maxItems: 2 + items: + minimum: 1 + maximum: 8 allOf: - if: @@ -81,12 +85,39 @@ allOf: - ti,dra7xx-phy-gmii-sel - ti,dm814-phy-gmii-sel - ti,am654-phy-gmii-sel + - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel then: properties: '#phy-cells': const: 1 description: CPSW port number (starting from 1) + - if: + properties: + compatible: + contains: + enum: + - ti,j7200-cpsw5g-phy-gmii-sel + then: + properties: + ti,qsgmii-main-ports: + maxItems: 1 + items: + minimum: 1 + maximum: 4 + + - if: + properties: + compatible: + contains: + enum: + - ti,j721e-cpsw9g-phy-gmii-sel + then: + properties: + ti,qsgmii-main-ports: + minItems: 2 + - if: not: properties: @@ -94,6 +125,7 @@ allOf: contains: enum: - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel then: properties: ti,qsgmii-main-ports: false
TI's J721e SoC supports additional PHY modes like QSGMII and SGMII that are not supported on earlier SoCs. Add a compatible for it. Extend ti,qsgmii-main-ports property to support selection of upto two main ports at once across the two QSGMII interfaces. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- .../bindings/phy/ti,phy-gmii-sel.yaml | 48 +++++++++++++++---- 1 file changed, 40 insertions(+), 8 deletions(-)