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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: iPGiO1u7j+LOF8Gfysix9p+CHyh7GDkRHjsrMLHS0LuiK52+PjTC+gXB8BIwgno5bORbr3SsFe0/EiF8i/2k1y2GMRdEnaupIH67SnlRqNTO73A1+V4T/+EBrPQG35SQMOk4I7GNJRaeZOd3L4q68QxRYrZIbCX63B7VzromqJq13cxSHkz/J3lniwqtAmFKdNViL8v5IVh9gnW4F2PY+PB9izeIrLth6dyvYkirYH4zDOm5YhSRZdmRHiFoYeSIPi7TfuPgTqR6Vu2aTBzLXL+9vaKeGpvDfWeSyn2euH55v2OZodLv3aL4tRwok2hFsaZjKCbfxwhOZl2EheVMxFD/4YAcCUPtG49SwuHIYjn29zFYxANwnYHT7h9dvT5BwEFCL7AZsNzT17gqBBHXgDLWbJEAhYUdg5Ihji2m8wCm9e2oo3OKXIcegmLqrTnOkPPJ6unVPKzFHPyg4UbgU1KcIWPBXFml84zhVni8hYUOZabZ6XrPn+QnZeXHp49I47vBq4fTiNbYlf2RWsjXKF61y9C/xGq6WIxM2Qz1l12M7ow6wM97mEr9znSzHOXxZfe5apexpEjxgpNRCojvLDEEBxsjkeArilu51jJyvVW3NRFhqj+9zs1tu9vRppGR13uNhKG/LAQUUrzYWnv/DsLHjII47Iy+N1h8preEkbguSbHPV+/QMiUpI+kAGcOqZazo5zSNw4qm1OKhf4vyzIZ4yihVECg1BSTwSIh8yznSeq7JrP6BNhOkOj7RbsGCDXBVm/DEP0SY/7bbFSsXx9Z535MolmxP0FlH5r84ZwCDfGftnncWlkJIHN0g98Ba4DbbWP7lcKVBUO1X84cViNCEA+TzKqxNXfEQ9KKnlI2DLRcKpuTLZrqqjzUzKo9HX8aGPdK87HWvUa8P7r5uh5M7cNhq5COjkBwxntqcYqc0wSOH/fMqYQ9PWWnqyelrjVoCGzFaYxexIit1Yv9vBxvGPaSQTeCgHYPeVa970ur+86XEIE+HU9YXZLZ6E06/ozC0XwHU2/oo8ySVzRu+TAPx7RP1zUJNfOMxHD0/xe403ouSIr097cXQPCUZvObSzraRlBBhr00W2WHlysEFvmpv/kalGwNmhLz0T7ZqJKk0N+PLRsKpmGDfJpln6L1oDBmt60Yi+CZME3BH/sVaNmwnHA4zRPgILexQbSI6yJcqB85rqQNYVQXkHMKpHWomLn1ewdWjn5TgpmarLUN+DOQv6DGbNeCurI40x04OmuEUloxhaSDWT3dbX5tTQHSmVtVBRYiboEgMEBP9GHVMH/VSdifNT9gHmVo3gYggjW+hk45sUIQ54LpllzYnLud7LChnQT5jgzql+GacTwQYxESF4WqBrOJb/W99X8Z/oMD3OhM2xW6B51+RId1k9RaespSPl8ITEgqAvyzzaa1ucnN5xiEFJ+l/WASTKCed76vc38T0mTtUwfBSwz0vxdTES0fgc2LIXRqJ8Z3/aB7Si0XvxPSZX4TODHHUBRJNMXfEeN3KaJSzR82JrHMYEhnt/nDPsXYRVpPGjA2fyflcrRl6R79L1aXQCGfSqwnUfA8PDmcn8XSLDlId9Z1z0KLo4ouyOAggJSfljpcPwDuolg== X-OriginatorOrg: seco.com X-MS-Exchange-CrossTenant-Network-Message-Id: 78fd30f7-b551-4040-97a0-08dab15e1a5a X-MS-Exchange-CrossTenant-AuthSource: DB7PR03MB4972.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2022 23:11:35.4939 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: oZc/4XVd/7RdhUQfTbt0YJ8Ah13erJYOnYjbcgGYGfFvpRA7tBIzkNr/ALqxB7EQgtLJdoURgxlKXo08rxSqLg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR03MB6421 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221018_161144_701351_D332B2AF X-CRM114-Status: GOOD ( 14.94 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This adds appropriate bindings for the macs which use the SerDes. The 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is no driver for this device (and as far as I know all you can do with the 100MHz clocks is gate them), so I have chosen to model it as a single fixed clock. Note: the SerDes1 lane numbering for the LS1046A is *reversed*. This means that Lane A (what the driver thinks is lane 0) uses pins SD1_TX3_P/N. Because this will break ethernet if the serdes is not enabled, enable the serdes driver by default on Layerscape. Signed-off-by: Sean Anderson --- This depends on [1]. [1] https://lore.kernel.org/netdev/20220804194705.459670-4-sean.anderson@seco.com/ (no changes since v6) Changes in v6: - XGI.9 -> XFI.9 Changes in v4: - Convert to new bindings .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 112 ++++++++++++++++++ drivers/phy/freescale/Kconfig | 1 + 2 files changed, 113 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index 7025aad8ae89..81d725a15e27 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -10,6 +10,8 @@ /dts-v1/; +#include + #include "fsl-ls1046a.dtsi" / { @@ -26,8 +28,110 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + clocks { + clk_100mhz: clock-100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk_156mhz: clock-156mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + }; }; +&serdes1 { + clocks = <&clk_100mhz>, <&clk_156mhz>; + clock-names = "ref0", "ref1"; + status = "okay"; + + /* + * XXX: Lane A uses pins SD1_RX3_P/N! That is, the lane numbers and pin + * numbers are _reversed_. In addition, the PCCR documentation is + * _inconsistent_ in its usage of these terms! + * + * PCCR "Lane 0" refers to... + * ==== ===================== + * 0 Lane A + * 2 Lane A + * 8 Lane A + * 9 Lane A + * B Lane D! + */ + serdes1_0: phy@0 { + #phy-cells = <0>; + reg = <0>; + + /* SGMII.6 */ + sgmii-0 { + fsl,pccr = <0x8>; + fsl,index = <0>; + fsl,cfg = <0x1>; + phy-type = ; + }; + }; + + serdes1_1: phy@1 { + #phy-cells = <0>; + reg = <1>; + + /* SGMII.5 */ + sgmii-1 { + fsl,pccr = <0x8>; + fsl,index = <1>; + fsl,cfg = <0x1>; + phy-type = ; + }; + }; + + serdes1_2: phy@2 { + #phy-cells = <0>; + reg = <2>; + + /* SGMII.10 */ + sgmii-2 { + fsl,pccr = <0x8>; + fsl,index = <2>; + fsl,cfg = <0x1>; + phy-type = ; + }; + + /* XFI.10 */ + xfi-0 { + fsl,pccr = <0xb>; + fsl,index = <0>; + fsl,cfg = <0x2>; + phy-type = ; + }; + }; + + serdes1_3: phy@3 { + #phy-cells = <0>; + reg = <3>; + + /* SGMII.9 */ + sgmii-3 { + fsl,pccr = <0x8>; + fsl,index = <3>; + fsl,cfg = <0x1>; + phy-type = ; + }; + + /* XFI.9 */ + xfi-9 { + fsl,pccr = <0xb>; + fsl,index = <1>; + fsl,cfg = <0x1>; + phy-type = ; + }; + }; +}; + + &duart0 { status = "okay"; }; @@ -140,21 +244,29 @@ ethernet@e6000 { ethernet@e8000 { phy-handle = <&sgmii_phy1>; phy-connection-type = "sgmii"; + phys = <&serdes1_1>; + phy-names = "serdes"; }; ethernet@ea000 { phy-handle = <&sgmii_phy2>; phy-connection-type = "sgmii"; + phys = <&serdes1_0>; + phy-names = "serdes"; }; ethernet@f0000 { /* 10GEC1 */ phy-handle = <&aqr106_phy>; phy-connection-type = "xgmii"; + phys = <&serdes1_3>; + phy-names = "serdes"; }; ethernet@f2000 { /* 10GEC2 */ fixed-link = <0 1 1000 0 0>; phy-connection-type = "xgmii"; + phys = <&serdes1_2>; + phy-names = "serdes"; }; mdio@fc000 { diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index a6ccccf9e39b..bcecbea72d31 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -54,6 +54,7 @@ config PHY_FSL_LYNX_10G depends on ARCH_LAYERSCAPE || PPC || COMPILE_TEST select GENERIC_PHY select REGMAP_MMIO + default y if ARCH_LAYERSCAPE help This adds support for the Lynx "SerDes" devices found on various QorIQ SoCs. There may be up to four SerDes devices on each SoC, and each