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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 98trJZPTKZ3Dmcsu4HtT7uwnMdlrgCb+WZPLUJwgkHy5geKm7IUSe4WTw74AEt2Esor6Gg19jL4EZQo5lncOZYGmly0MP8yHhSwir9jHK7farvJM7tmEe9kjWVh7KV9gReByQqZB+o6xmQQBTF/vg+lmn1gXU3AHx/PuWqrvyHBdgkgUJ4yXK8CSQTZErqpURcve50hVSeMIyfbl5aK1F2h12pmsebS0y6uAsDCk5Y/bk8iaN2rxkxlyRxOoCvR7EwH3RFk1U89iGUm756HB4HOHdzgrh6uQM27NGcggZv+3Lp0oQdu2v0H/DTjQ5EozGWfIcpiK0557ax0G/hoYRaq/b0cJTYq65E20T+qYL0ZxoAI2+OIrxp8zLq7P7mtmKAe9BMiHIehrlCI3q3wTHO1a3TYjAO5NZD7uQi35RyMQptQzXM9cW0JWDNFU1LXcPAi/tIwD6SbwJ/JCZCS9hYzW9NGczDEB83LXbWh2FBtB6aGaBBG5hVhFV8L/uMCUJ2smsjEnBmPZKjm0w/XRpNrDLtjiVfczp9Avgd6v+u6OSEGYLZIjtjgQ730dlnIPahzQvqfdUuumqbGrY0obDhvPVSpByL7EGbIXOBHKbgip4PYISTqOTalP35X6uIGP9QqWNhPKx429bja7U3U8ucG55192xyy1gKQLOtQkLpQY9MJdV45GmC3WUanxqWnu8vLCL1W3QLxubj+DPTPGSZtwMJ+9cqiUHSRmgsBw763nbmQECi4y3TmFAoh25TlWHedoZkrUy/dJBGkU0V9eqCX1UIne7Z8HuEwTxrIgwA1/JbLopAKgd6y2wrvA66tVs3w6ky6UARe2QDrUGJFl17hthUYr7fm3iHWeFj/0e4Xqjagalxccd5+xcJuRYxQCwDXzBlBNibNBkC9UNpbLV18/n3qvcT1b5wS4Zbp1XDYn3HF0qdG4AUWlXNNW2Kff8LBBT0LHk17FbdvCh9DYRXCMuO0g/bSS5cws8J9HWdoNris4+Vq3+n3SmvFkGHw2wXexbhA9ljrO7CPKeB++cEuATxQWQfYo5wnNw6zCHwJF5Mku0a/h4dm5o0w6sW9/Xj5rapLQs6n/o32hpiI0dnW/Xu7HxSRUKwHL+cjArGmWrRIIVUfsKSxhnqXMoRuuWYyxR65jEuBMtmVKv1yo5ZozofWU/IIL2OVWzkdlwWEOpXj9xBdh8Ha9DLuw3CIPI+myQBBbmjjZHUMfvFlbZmmvcQdw6l026Z+9pAZKO7blKi8V5Jtvtl3qCcc+t/VTVT+xXcGd9vpzqsFWisTFfYUDgJuXVcZbeBzFlbLb+fV9UTnx5+3nEWCMrOPjc5bIJhZdRTQ0gQl+q/qzuFkgDHzCAV7G57l0/ZdwTci8BxW0CH0T+kNi7DdZQJW1vC5pMrBqwa5FozV064CKuSNxeDMbU52xTcR81ocsR9Ac8FGxIPDORlSk7BI7GuXfY/SZbBEzRpPTIck59QTGlj5Ova+YaC7W0Qwmaq6QMHo5zHh8dswmBeJnGYkW0PNhCm1akzuTnGPQtyoOv3S5tEiOGi1qTDWOEUgJhKiGt6RehNiBYIfdY7GTnPjJm9hL2NV1KRm44tlCBm5c6KhVRLYsmQ== X-OriginatorOrg: seco.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6a2cd09a-579b-4e41-611d-08dab15e1b4b X-MS-Exchange-CrossTenant-AuthSource: DB7PR03MB4972.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2022 23:11:37.1032 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9AAmZlzBIr4fRD1u3LB8tcJcufu+kW0L2nsTozSc9YyWUiddYwxQBc8ypAkjn45sMi8OIiDIg3lzyrTHMcDDJw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR03MB6421 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221018_161146_989537_341B13AA X-CRM114-Status: GOOD ( 12.75 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This is a first stab at adding serdes support on the LS1088A. Linux hangs around when the serdes is initialized if the si5341 is enabled, so it's commented out. The MC firmware needs to be fairly new (it must support DPAA2_MAC_FEATURE_PROTOCOL_CHANGE), and the DPC needs to set the macs to MAC_LINK_TYPE_BACKPLANE. For this reason, I think this will be difficult to do in a backwards-compatible manner. I have not finished testing this, but hopefully it can be a good starting point. Signed-off-by: Sean Anderson --- (no changes since v4) Changes in v4: - Convert to new bindings .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 161 ++++++++++++++++++ 1 file changed, 161 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 1bfbce69cc8b..5c502048d887 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -10,17 +10,138 @@ /dts-v1/; +#include + #include "fsl-ls1088a.dtsi" / { model = "LS1088A RDB Board"; compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; + + clocks { + si5341_xtal: clock-48mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + clk_100mhz: clock-100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk_156mhz: clock-156mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + }; + + ovdd: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "ovdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + dvdd: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "dvdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + +}; + +&serdes1 { + //clocks = <&si5341 0 8>, <&si5341 0 9>; + clocks = <&clk_100mhz>, <&clk_156mhz>; + clock-names = "ref0", "ref1"; + status = "okay"; + + serdes1_0: phy@0 { + #phy-cells = <0>; + reg = <0>; + + /* SG2 */ + sgmii-3 { + fsl,pccr = <0x8>; + fsl,index = <3>; + fsl,cfg = <0x1>; + phy-type = ; + }; + + /* XFI2 */ + xfi-1 { + fsl,pccr = <0xb>; + fsl,index = <1>; + fsl,cfg = <0x1>; + phy-type = ; + }; + }; + + serdes1_1: phy@1 { + #phy-cells = <0>; + reg = <1>; + + /* SG1 */ + sgmii-2 { + fsl,pccr = <0x8>; + fsl,index = <2>; + fsl,cfg = <0x1>; + phy-type = ; + }; + + /* + * XFI2 + * Table 23-1 and section 23.5.16.4 disagree; this reflects the + * table. + */ + xfi-0 { + fsl,pccr = <0xb>; + fsl,index = <0>; + fsl,cfg = <0x1>; + phy-type = ; + }; + }; + + serdes1_2: phy@2 { + #phy-cells = <0>; + reg = <2>; + + /* QSGb */ + qsgmii-1 { + fsl,pccr = <0x9>; + fsl,index = <1>; + fsl,cfg = <0x1>; + phy-type = ; + }; + }; + + serdes1_3: phy@2 { + #phy-cells = <0>; + reg = <2>; + + /* QSGa */ + qsgmii-0 { + fsl,pccr = <0x9>; + fsl,index = <0>; + fsl,cfg = <0x1>; + phy-type = ; + }; + }; +}; + +&dpmac1 { + phys = <&serdes1_1>; }; &dpmac2 { phy-handle = <&mdio2_aquantia_phy>; phy-connection-type = "10gbase-r"; pcs-handle = <&pcs2>; + phys = <&serdes1_0>; }; &dpmac3 { @@ -28,6 +149,7 @@ &dpmac3 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_0>; + phys = <&serdes1_3>; }; &dpmac4 { @@ -35,6 +157,7 @@ &dpmac4 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_1>; + phys = <&serdes1_3>; }; &dpmac5 { @@ -42,6 +165,7 @@ &dpmac5 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_2>; + phys = <&serdes1_3>; }; &dpmac6 { @@ -49,6 +173,7 @@ &dpmac6 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_3>; + phys = <&serdes1_3>; }; &dpmac7 { @@ -56,6 +181,7 @@ &dpmac7 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_0>; + phys = <&serdes1_2>; }; &dpmac8 { @@ -63,6 +189,7 @@ &dpmac8 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_1>; + phys = <&serdes1_2>; }; &dpmac9 { @@ -70,6 +197,7 @@ &dpmac9 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_2>; + phys = <&serdes1_2>; }; &dpmac10 { @@ -77,6 +205,7 @@ &dpmac10 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_3>; + phys = <&serdes1_2>; }; &emdio1 { @@ -142,6 +271,38 @@ i2c-switch@77 { #address-cells = <1>; #size-cells = <0>; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + si5341: clock-generator@74 { + #address-cells = <1>; + #clock-cells = <2>; + #size-cells = <0>; + compatible = "silabs,si5341"; + reg = <0x74>; + clocks = <&si5341_xtal>; + clock-names = "xtal"; + vdd-supply = <&ovdd>; + vdda-supply = <&dvdd>; + vddo8-supply = <&ovdd>; + vddo9-supply = <&ovdd>; + silabs,iovdd-33; + status = "disabled"; + + out@8 { + reg = <8>; + silabs,format = <1>; + }; + + out@9 { + reg = <9>; + silabs,format = <1>; + }; + }; + }; + i2c@2 { #address-cells = <1>; #size-cells = <0>;