| Message ID | 20221026074532.109220-4-s-vadapalli@ti.com |
|---|---|
| State | Accepted |
| Commit | 1eaf0d2507b850469de23b38c06f170dfeda24a3 |
| Headers | show |
| Series | Add support to PHY GMII SEL for J721e CPSW9G QSGMII | expand |
On 26/10/2022 10:45, Siddharth Vadapalli wrote: > Each of the CPSW9G ports in J721e support additional modes like QSGMII. > Add a new compatible for J721e to support the additional modes. > > In TI's J721e, each of the CPSW9G ethernet interfaces can act as a > QSGMII main or QSGMII-SUB port. The QSGMII main interface is responsible > for performing auto-negotiation between the MAC and the PHY while the rest > of the interfaces are designated as QSGMII-SUB interfaces, indicating that > they will not be taking part in the auto-negotiation process. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> > --- > drivers/phy/ti/phy-gmii-sel.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c > index c8f30d2e1f46..8c667819c39a 100644 > --- a/drivers/phy/ti/phy-gmii-sel.c > +++ b/drivers/phy/ti/phy-gmii-sel.c > @@ -218,6 +218,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = { > .num_qsgmii_main_ports = 1, > }; > > +static const > +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { > + .use_of_data = true, > + .regfields = phy_gmii_sel_fields_am654, > + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), > + .num_ports = 8, > + .num_qsgmii_main_ports = 2, > +}; > + > static const struct of_device_id phy_gmii_sel_id_table[] = { > { > .compatible = "ti,am3352-phy-gmii-sel", > @@ -243,6 +252,10 @@ static const struct of_device_id phy_gmii_sel_id_table[] = { > .compatible = "ti,j7200-cpsw5g-phy-gmii-sel", > .data = &phy_gmii_sel_cpsw5g_soc_j7200, > }, > + { > + .compatible = "ti,j721e-cpsw9g-phy-gmii-sel", > + .data = &phy_gmii_sel_cpsw9g_soc_j721e, > + }, > {} > }; > MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table); cheers, -roger
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index c8f30d2e1f46..8c667819c39a 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -218,6 +218,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = { .num_qsgmii_main_ports = 1, }; +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { + .use_of_data = true, + .regfields = phy_gmii_sel_fields_am654, + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), + .num_ports = 8, + .num_qsgmii_main_ports = 2, +}; + static const struct of_device_id phy_gmii_sel_id_table[] = { { .compatible = "ti,am3352-phy-gmii-sel", @@ -243,6 +252,10 @@ static const struct of_device_id phy_gmii_sel_id_table[] = { .compatible = "ti,j7200-cpsw5g-phy-gmii-sel", .data = &phy_gmii_sel_cpsw5g_soc_j7200, }, + { + .compatible = "ti,j721e-cpsw9g-phy-gmii-sel", + .data = &phy_gmii_sel_cpsw9g_soc_j721e, + }, {} }; MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table);
Each of the CPSW9G ports in J721e support additional modes like QSGMII. Add a new compatible for J721e to support the additional modes. In TI's J721e, each of the CPSW9G ethernet interfaces can act as a QSGMII main or QSGMII-SUB port. The QSGMII main interface is responsible for performing auto-negotiation between the MAC and the PHY while the rest of the interfaces are designated as QSGMII-SUB interfaces, indicating that they will not be taking part in the auto-negotiation process. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- drivers/phy/ti/phy-gmii-sel.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)