| Message ID | 20221229115932.3312318-2-dmitry.baryshkov@linaro.org |
|---|---|
| State | Accepted |
| Commit | a98f5cc9c0e01186244498a084bf24ae764f86f2 |
| Headers | show |
| Series | phy: qualcomm: pcie2: register as clock provider | expand |
On 29/12/2022 12:59, Dmitry Baryshkov wrote: > Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format > from the text description. You got here Rob's tag. Best regards, Krzysztof
On 29/12/2022 16:01, Krzysztof Kozlowski wrote: > On 29/12/2022 12:59, Dmitry Baryshkov wrote: >> Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format >> from the text description. > > You got here Rob's tag. True, missed it To save a repost: Reviewed-by: Rob Herring <robh@kernel.org> For the reference: https://lore.kernel.org/all/167209187655.72399.4038954760167968816.robh@kernel.org/
On Thu, 29 Dec 2022 13:59:31 +0200, Dmitry Baryshkov wrote: > Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format > from the text description. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../bindings/phy/qcom,pcie2-phy.yaml | 86 +++++++++++++++++++ > .../bindings/phy/qcom-pcie2-phy.txt | 42 --------- > 2 files changed, 86 insertions(+), 42 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml > delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221229115932.3312318-2-dmitry.baryshkov@linaro.org phy@7786000: '#clock-cells' is a required property arch/arm64/boot/dts/qcom/qcs404-evb-1000.dtb arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb
On Fri, 30 Dec 2022 at 18:34, Rob Herring <robh@kernel.org> wrote: > > > On Thu, 29 Dec 2022 13:59:31 +0200, Dmitry Baryshkov wrote: > > Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format > > from the text description. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > .../bindings/phy/qcom,pcie2-phy.yaml | 86 +++++++++++++++++++ > > .../bindings/phy/qcom-pcie2-phy.txt | 42 --------- > > 2 files changed, 86 insertions(+), 42 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml > > delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt > > > > Running 'make dtbs_check' with the schema in this patch gives the > following warnings. Consider if they are expected or the schema is > incorrect. These may not be new warnings. > > Note that it is not yet a requirement to have 0 warnings for dtbs_check. > This will change in the future. > > Full log is available here: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221229115932.3312318-2-dmitry.baryshkov@linaro.org > > phy@7786000: '#clock-cells' is a required property > arch/arm64/boot/dts/qcom/qcs404-evb-1000.dtb > arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb The fix was a part of the v1 of the series and was picked by Bjorn already: https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/commit/?h=arm64-for-6.3&id=977e9262c3542e87b513d4dad4c57b2c85e16c8c
diff --git a/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml new file mode 100644 index 000000000000..dbc4a4c71f05 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCIe2 PHY controller + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm + platforms. + +properties: + compatible: + items: + - const: qcom,qcs404-pcie2-phy + - const: qcom,pcie2-phy + + reg: + items: + - description: PHY register set + + clocks: + items: + - description: a clock-specifier pair for the "pipe" clock + + clock-output-names: + maxItems: 1 + + "#clock-cells": + const: 0 + + "#phy-cells": + const: 0 + + vdda-vp-supply: + description: low voltage regulator + + vdda-vph-supply: + description: high voltage regulator + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: pipe + +required: + - compatible + - reg + - clocks + - clock-output-names + - "#clock-cells" + - "#phy-cells" + - vdda-vp-supply + - vdda-vph-supply + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-qcs404.h> + phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; +... diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt deleted file mode 100644 index 30064253f290..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt +++ /dev/null @@ -1,42 +0,0 @@ -Qualcomm PCIe2 PHY controller -============================= - -The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm -platforms. - -Required properties: - - compatible: compatible list, should be: - "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" - - - reg: offset and length of the PHY register set. - - #phy-cells: must be 0. - - - clocks: a clock-specifier pair for the "pipe" clock - - - vdda-vp-supply: phandle to low voltage regulator - - vdda-vph-supply: phandle to high voltage regulator - - - resets: reset-specifier pairs for the "phy" and "pipe" resets - - reset-names: list of resets, should contain: - "phy" and "pipe" - - - clock-output-names: name of the outgoing clock signal from the PHY PLL - - #clock-cells: must be 0 - -Example: - phy@7786000 { - compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; - reg = <0x07786000 0xb8>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc GCC_PCIE_0_PIPE_ARES>; - reset-names = "phy", "pipe"; - - vdda-vp-supply = <&vreg_l3_1p05>; - vdda-vph-supply = <&vreg_l5_1p8>; - - clock-output-names = "pcie_0_pipe_clk"; - #clock-cells = <0>; - #phy-cells = <0>; - };
Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format from the text description. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../bindings/phy/qcom,pcie2-phy.yaml | 86 +++++++++++++++++++ .../bindings/phy/qcom-pcie2-phy.txt | 42 --------- 2 files changed, 86 insertions(+), 42 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt