| Message ID | 20230113212138.421583-2-dmitry.baryshkov@linaro.org |
|---|---|
| State | Accepted |
| Commit | 0dcaef53eb9a1cbafd1ae54187b8fed152c3a41c |
| Headers | show |
| Series | [1/2] phy: qcom-qmp-pcie: fix the regs layout table for sm8450 gen3x1 PHY | expand |
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index e1f038cc173b..a49711c5a63d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -1862,7 +1862,7 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v4_usb3phy_regs_layout, + .regs = qmp_v5_usb3phy_regs_layout, .pcs_usb_offset = 0x1000, .has_pwrdn_delay = true,
The sdx64 uniphy gen3x1 PHY references the qmp_v4_usb3phy_regs_layout while the PHY itself uses v5 regs. While there are only minor differences between v4 and v5 regs and none of them concerns registers mentions in regs_layout, switch the PHY to use qmp_v5_usb3phy_regs_layout, to remove possible confusion. Fixes: 14d98d3bf70e ("phy: qcom-qmp-usb: fix regs layout arrays") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)