From patchwork Sat Jan 14 07:10:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13101872 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5E1BC677F1 for ; Sat, 14 Jan 2023 07:11:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=m8C/sDpO6Q7YdxifwpbSb5cPkZ9wVeiotv0gPMJn54k=; b=bofTl7RIEbXpQE RqCtpd/SMGQWh5uYm23o1MQAKkujQi8CZMla6O6GJEmNfc7rV8Im6VFqTHAJwWiZ8XxoL7RQwUA71 oyJsFeY85m02mZVfTBee6vbzPWziDZuFhptJvEfHOoD37xTGIuDjA37TBvcQaMNiSrLOJj5XHEYPP xT4h9gJr7opcSWklGGcZThv/XsdKf2IAMQapS1PBgZMGpmYNhGa1vAhnZ13ZgbnRbHGLVdrfERskX 5vAL8haFG981NTLEaexkWpPOh6jqIhAfNsjqRVMqNC3UKiJc34q25G70Aa3JhXZSH1B09twWL8yAl 6wtsnxXhxibNr17gVQTQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pGagv-005OFZ-6S; Sat, 14 Jan 2023 07:11:01 +0000 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pGags-005OEe-JW for linux-phy@lists.infradead.org; Sat, 14 Jan 2023 07:10:59 +0000 Received: by mail-pj1-x102a.google.com with SMTP id z4-20020a17090a170400b00226d331390cso26487142pjd.5 for ; Fri, 13 Jan 2023 23:10:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zF/lP8i6/bvX2WOvYdvQtXMAtlIxWZ4/WtUnoDch0P4=; b=pXIXVySKf8INquka7iLKSXPe66fspzDGSvWYIshcF8iETrjM7PY0FKIzwmBCqtzqja hwGoIZfzKwyp/4jUUdR7l4rxIBZVhPNlyT21eZDA1gAwX4Mvg47uXQDtBGZRwLwInqnu siM+WFYtXYg7NG2mIoQE9LN4Fd43WA1/VWLJwT0xwXjG6LqUmu8qV3jwqV5wQs43BpWh S8AYdys5rozikW914ueqrGaU8+NjxzgFw2HYzK0VX+NKAfdoICYc1kvvqDI+JoN3rTjz J3svM+VIrmNsbTNz+qrQ9+xQFuv6p01qlZVwDVKIWkYPmpO9A5YFsyLT2EgFfVPUL0OU d8mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zF/lP8i6/bvX2WOvYdvQtXMAtlIxWZ4/WtUnoDch0P4=; b=JvQqc0EbQc8G5Uycg6Cr5ip9e7xOlopIDuTcpz2vlsVCMNKng/YyI0uWB6RpRi1Qil LGkXFsTaZGocG2RUyUq+Ea+XII1EsqQ1Ej0Kmte5nq69xatEGA/mi/tJ4nnHT4xNkLif nuX/bSGP2y+EoNoAL0vK8fzU0VYZHIXNHIN9Cb3sWQoVDEpxJFQ2XrWG1qAyV0qZF9i5 ixupcVR2mQwK9xGLulT7VT+z/Fv8wsauIpPkTcuJcJ+pgi8ke3kM8QvfKBrgE/gIXDIY +17DhGvKjS083yNVtI3tR9Ur3Q/nrQKYr37cbm/LvcT1yLF60QMJKsumx5igHIY2664t xPEA== X-Gm-Message-State: AFqh2kp5z/yJWjccet62hB+wZAsVy4KKece+gquFAdWj9T0XUvKqPXmt CkFV72lKmGr6+YfkFbbrlS1BwILkRAx0YXs= X-Google-Smtp-Source: AMrXdXtT3Pmw0+Gtll6XZhsbkX9VbgMkkfUCA5LcR4JJsXbq1T9WjYqU7jhuoQ4hXpFUoeixu4YRNg== X-Received: by 2002:a05:6a20:1586:b0:9d:efd3:66c1 with SMTP id h6-20020a056a20158600b0009defd366c1mr116328768pzj.8.1673680257307; Fri, 13 Jan 2023 23:10:57 -0800 (PST) Received: from localhost.localdomain ([220.158.159.156]) by smtp.gmail.com with ESMTPSA id q10-20020a170902e30a00b00192a04bc620sm15225358plc.295.2023.01.13.23.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 23:10:56 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 10/12] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoC Date: Sat, 14 Jan 2023 12:40:07 +0530 Message-Id: <20230114071009.88102-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230113_231058_659990_0EF7E611 X-CRM114-Status: UNSURE ( 8.46 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org UFS PHY in SM8350 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 421359ca62ba..b784eed2eb1f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -576,6 +576,34 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + struct qmp_ufs_offsets { u16 serdes; u16 pcs; @@ -882,6 +910,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .serdes = sm8350_ufsphy_hs_b_serdes, .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 = { + .tx = sm8350_ufsphy_g4_tx, + .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx = sm8350_ufsphy_g4_rx, + .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs = sm8350_ufsphy_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l,