From patchwork Sat Jan 14 07:10:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13101869 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22B15C46467 for ; Sat, 14 Jan 2023 07:10:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aInJRsyp1Q6MGuFFgbG3/z/t9pik3r7wgr8Vn49PtTU=; b=YlOmFhsBsI/MkA 4Rb8lrt5+O1UlhoyCbCiFPz0+WBDAxnQPM7qDbWuV5a87tXEofFnu7CCEUEQMfXipBZTgVDJuUg7f whqCKoWlu78RmrIW36fTj/wEgCPIR70ec01hX/6rzMVb/kXC7eEJNur0xXEp479owtCzXj5RW61zO 9JJhaGXEicYcUhiN/XvwqUKIzTM6qWVMfOvmtdBDgSRitz9uYTOFWXBoNsmWT7xuQ+qe3xJ+RoRBx yGUAG77seOX8kxTKFTm3oS19uqTzoxP204cD2QyhFlwlNld6OBCMsblF/+upB/927qEiQucbjgw08 UjCWrUE7fc0ea5N2uTCg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pGagi-005OCe-J8; Sat, 14 Jan 2023 07:10:48 +0000 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pGagf-005OBu-C9 for linux-phy@lists.infradead.org; Sat, 14 Jan 2023 07:10:46 +0000 Received: by mail-pl1-x633.google.com with SMTP id b17so18058196pld.7 for ; Fri, 13 Jan 2023 23:10:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1ATjbzDQlL4OA8nxAfb65uZnNVJqa+ucbbND1K754XE=; b=G1+dzuweYveFF3fKUfyYg3EkQcvxBV0KRGC0MJUNNuksus2io5QwA7JLyjvyA72rD3 wWroFh0PLCngGG2+bT3muP1yl3ThO35CKRUDsK0ZrhRqZhWLogXHig4SWwtcQ7Oa/MV/ vouHQV0hUAX/vRy1qQOaKHNI/mxZRAO6Ms0Op6yKvd1cMcLDW1Z+6b9FUxrCVpFcXP33 d6N/H++CVuYXQyY3ru7F6pTLhLk8wULsAtDp3o5U7QaxE1z+FTfGi6uuRVmo9d4l3YCb K2lqUqa/sxg9VDFvTNzqg8pEfySD1YmMVuya/0mvlKMpIbs1hGNS9CstURh2lZVDgun/ c/0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1ATjbzDQlL4OA8nxAfb65uZnNVJqa+ucbbND1K754XE=; b=Ujyf5KEtKc/V81UYr8/8UK3lbR6G5VZs5RW24VUm0iDebWP4Iy6+5R6Q/e0zprzmwF LpcKysmvhMaiOZfdeJfyCq8lMWUnGpt8D3Ej8a0KTXx/gfqGmO8iTDVVYndC4KriRzgL q8VaUHrrJOYynekNqlS8om/c+D8WwYHEXGje5yj09DzBLRzbLihLESYUXCp4IPHNWTLC Xrvm5PkN5upPJDesWUoMSuM1KXZ9covIA/42UHjmLAi9K0IGgj2m4o0GD9rsvdsNWE8q ZpLQ//mv2egTTfvi2XG53nGOf/ZkDJqdvzOcxh1mF9d6wKTm1PIwLLPdiJI0QYdGPo2l 7rTg== X-Gm-Message-State: AFqh2kqHxdYhzygOFgLBkIhNd6azI3yc1bfn82bihYQLNBwRuaKKZrBh tqSoAyHUcj1OTrfCWxb+yT4/ X-Google-Smtp-Source: AMrXdXvBpTYHPiP++Mc3y3ojNQYS8b/MPAxDAUf7rAX1UvKR0ZXahFIIDvYIzHQfZ5/Vt9I4kP5E8A== X-Received: by 2002:a17:902:c497:b0:193:3845:de53 with SMTP id n23-20020a170902c49700b001933845de53mr21809874plx.39.1673680244828; Fri, 13 Jan 2023 23:10:44 -0800 (PST) Received: from localhost.localdomain ([220.158.159.156]) by smtp.gmail.com with ESMTPSA id q10-20020a170902e30a00b00192a04bc620sm15225358plc.295.2023.01.13.23.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 23:10:43 -0800 (PST) From: Manivannan Sadhasivam To: vkoul@kernel.org Cc: andersson@kernel.org, quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v6 07/12] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoC Date: Sat, 14 Jan 2023 12:40:04 +0530 Message-Id: <20230114071009.88102-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> References: <20230114071009.88102-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230113_231045_431662_55BD9410 X-CRM114-Status: UNSURE ( 8.15 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index a7261744f971..57d0744d18c2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -379,6 +379,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), @@ -416,6 +420,25 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), }; +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), @@ -426,6 +449,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -769,6 +797,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .serdes = sm8150_ufsphy_hs_b_serdes, .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 = { + .tx = sm8150_ufsphy_hs_g4_tx, + .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), + .rx = sm8150_ufsphy_hs_g4_rx, + .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), + .pcs = sm8150_ufsphy_hs_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l,