@@ -414,18 +414,27 @@ &pcie_1_phy_aux_clk {
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_state>;
+
status = "okay";
};
&pcie0_phy {
vdda-phy-supply = <&vreg_l1e_0p88>;
vdda-pll-supply = <&vreg_l3e_1p2>;
+
status = "okay";
};
&pcie1 {
wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>;
+
status = "okay";
};
@@ -433,6 +442,7 @@ &pcie1_phy {
vdda-phy-supply = <&vreg_l3c_0p91>;
vdda-pll-supply = <&vreg_l3e_1p2>;
vdda-qref-supply = <&vreg_l1e_0p88>;
+
status = "okay";
};
@@ -1672,25 +1672,24 @@ pcie0: pci@1c00000 {
<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
- <&gcc GCC_PCIE_0_AUX_CLK>,
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
- clock-names = "pipe",
- "aux",
+ clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"ddrss_sf_tbu",
- "aggre0";
+ "noc_aggr";
- interconnect-names = "pcie-mem";
- interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
iommus = <&apps_smmu 0x1400 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
@@ -1704,12 +1703,6 @@ pcie0: pci@1c00000 {
phys = <&pcie0_phy>;
phy-names = "pciephy";
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_default_state>;
-
status = "disabled";
};
@@ -1771,8 +1764,7 @@ pcie1: pci@1c08000 {
<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
- <&gcc GCC_PCIE_1_AUX_CLK>,
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
@@ -1780,21 +1772,21 @@ pcie1: pci@1c08000 {
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
- clock-names = "pipe",
- "aux",
+ clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"ddrss_sf_tbu",
- "aggre1",
- "cnoc_pcie_sf_axi";
+ "noc_aggr",
+ "cnoc_sf_axi";
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
- interconnect-names = "pcie-mem";
- interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
iommus = <&apps_smmu 0x1480 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
@@ -1802,20 +1794,13 @@ pcie1: pci@1c08000 {
resets = <&gcc GCC_PCIE_1_BCR>,
<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
- reset-names = "pci",
- "pcie_1_link_down_reset";
+ reset-names = "pci", "link_down";
power-domains = <&gcc PCIE_1_GDSC>;
phys = <&pcie1_phy>;
phy-names = "pciephy";
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- enable-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pcie1_default_state>;
-
status = "disabled";
};
@@ -1823,18 +1808,17 @@ pcie1_phy: phy@1c0e000 {
compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
reg = <0x0 0x01c0e000 0x0 0x2000>;
- clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&tcsr TCSR_PCIE_1_CLKREF_EN>,
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
- <&gcc GCC_PCIE_1_PIPE_CLK>,
- <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
+ <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "rchng",
- "pipe", "aux_phy";
+ "pipe";
resets = <&gcc GCC_PCIE_1_PHY_BCR>,
<&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
- reset-names = "phy", "nocsr";
+ reset-names = "phy", "phy_nocsr";
assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
First, move the pinctrl related propeties out from SoC dtsi and into the board dts and add blank lines before status properties in the PHY nodes to be consistent with the rest of the nodes. Then drop the pipe clock from the controller nodes. Rename the aggre0 and aggre1 clocks to more generic noc_aggr, and then the cnoc_pcie_sf_axi to cnoc_sf_axi. Add the cpu-pcie interconnects to both controller nodes. Rename the pcie1 second reset to link_down and drop the unnecessary enable-gpios. Switch the aux clock to GCC_PCIE_1_PHY_AUX_CLK for the pcie1 PHY and drop the aux_phy from clock-names. Also rename the nocsr reset to phy_nocsr. With this changes we are now in line with the SC8280XP bindings. Fixes: 98a4dc3a78fa ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> --- The v8 of this patch is: https://lore.kernel.org/all/20230206212619.3218741-12-abel.vesa@linaro.org/ Changes since v8: * added Johan's R-b tag arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 10 +++++ arch/arm64/boot/dts/qcom/sm8550.dtsi | 52 +++++++++---------------- 2 files changed, 28 insertions(+), 34 deletions(-)