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Miller" , Florian Fainelli , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v1 net-next 3/7] net: mscc: ocelot: expose ocelot_pll5_init routine Date: Wed, 15 Feb 2023 23:53:17 -0800 Message-Id: <20230216075321.2898003-4-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216075321.2898003-1-colin.foster@in-advantage.com> References: <20230216075321.2898003-1-colin.foster@in-advantage.com> X-ClientProxiedBy: BY3PR05CA0019.namprd05.prod.outlook.com (2603:10b6:a03:254::24) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWHPR1001MB2351:EE_|IA1PR10MB5993:EE_ X-MS-Office365-Filtering-Correlation-Id: 88e1b277-ffd3-4b79-99e6-08db0ff2ea20 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OHMAkuAuUFmRZ5IOSNlGlZqidXCpIJ7SpvQEUP9emxW0PMyfAXuVaPYcJvh2ptjPWIqMTNYZgFjobRMeo8nUxwAq368YcveJbJaryrddX3uNPtT8u2xVKCsevXt5USXZ8wS8Sg5Sp4tRc1Ha7QGYFC0j5Yqb3GaAvmfdDJCcM89ENNOYN0IGJH/NOCKoviwfM7cxC73emjQRzqH4gYKGhoWv25PGUy9Dg/OcKiDxY4nmU8BEoEKHZtAcrr+TKVzjP6Jn0CI3123H7reqfrJifU6woYh7pfFRBPn2+TGuhD+6jEji4LEWhjFVElFvz1SRbkoHJTCffkpVOV1qtSWqDGHlt8bB0grb7QE4VOS63uU4MluX9Hwn/sQ3QlKsdC2X++13H5fC0lW8PkVpx/clMfnCaiR+H4CadrNW81UmYrz2fKe2CEzX2ldjmFUkR/CyU808CL2vIzPVncVeUrxrIzSBZjCjlZ/R+49WqhvoyCZasfBGEXvPzuvikKB6FPjTx0Nc4BcYb0y2Lc1dcG56a4OTYSVXkm6yLrxJAk38Zjc459lecb+kHc5vNhB7fPLI7kZcMllk5LpYZemEc54y6RolnNQcBu30KxVlQlRJHnkFCDFLZsW4PGx9w5usU97qQlpkhWcwDSIu7FsHhA+2jrx0rY6pDSV6nRmZ38Qki/gwzYi4K9YsDw4hqUnyC8hKrkOYUdyGYTaiFtrO5WI/vQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(136003)(39830400003)(396003)(366004)(346002)(376002)(451199018)(83380400001)(5660300002)(38350700002)(41300700001)(2906002)(8936002)(38100700002)(2616005)(6506007)(26005)(6512007)(186003)(6666004)(478600001)(52116002)(6486002)(44832011)(1076003)(86362001)(316002)(66476007)(66946007)(54906003)(4326008)(8676002)(66556008)(7416002)(36756003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +WEVOQDyQ4t00rnmhW8bslH1TBlBZDsvupAF9+zeMEoKQ8nsZFuvUTy164NZqXGPAo4fN3xUcEAq5n9TSHkAUEAHHMOPb63SH8vSjzjdegznstOuSi+m7E0I3c8HSKB2VtDrVl/D+sy9oH06o8akQftP1m48ureMJAIB9NoS1ZiMzgyd1FwrWLasiotskmKu6kfxQdk7AyMG9hhiXonZnwSLWHTEmD5y4OxQ0jXVMyu7bfHHFnRNiSetY68yDL3bBQ4xCyBz2mM67p5iWbb6EnegQq9yxGIGxzVi00OaWVbek6w84IvkG1V9m9wYlfrjl0J9TDUIRXzpmHRqV7Yn3br1rJDHVsgRsJFsbx4wNcxo5viwSNCPFnv9ZSXgGSe8yoltt10BOo0MpmfPLYw47MzQmEEjUp648wUGMkd6/k12qseQzrWZlXaDR8pqjoCq3TXUYLpZRM2jupQQvPnuYJe7ijYPb1H7wcEA+Wf62yeefQkGI83VpdzBEBrjl6Oa3Wbi55PXvzvgenL/X0eDIBFFUzulv0Dpd4N54ueKkoHsz4qgBDrPRJqEX67r3/XwrHQMsC0L5pokmZfnaZpquYso5Fmmcbjn/va9yFhziwO6dy7iNNa1XaQ9QvvG6kum+Eulzymrit/pcDIS8EKU4k7Ys8etL69RXabLvAv2ezQ3ZXLarJv9aGjHVrt3jt79hoCKux79yP5W5Rg5ITQACKgBIAETgh+Uc2vTSZ1/THAe6EsIctI57+dCIrUOfETEL2is8oQf83+CtL7TtJxe2uC1mH4JF4i9xQYmTuH2oSNyL7SPiT6X/bXNyl6ACXiuijpL6uh68cRcbMwA6LlgHndMQLiODUkz97NpuCiqtjPF1YK23faxtnNZcH2s8N0AewkFQUo5SHqS/aXaU6Un+9BMiH+imp1NkIF155wPZ/+WAj9r+DeGQNs0r0Y91eH/RCel5swgAu5SIv0vgeSMg5HYzNAqACPI9bWuWuHKDUiM9p8wu+4NZ0z9T3s6Q/xLTjoeau1C3EBWty8Q2EMYmHwIKRDy684Y8iJEe8Rc36JVwErzUHPyhjReWRexxyrFV/GhrZPxzc8BYJHNQI4naYmLqBLcZFt5xb2/VMcZZiVOajmxTg/qhAU7EwNQSgOGjaDs1q5sdhgHLx5O0MfYmKUPJcCBKveW6y7588G6Zf+6OSGHvl6R88sI1cy1G7NJ8hQaA2qH8Dpg4YKRxCOdYb1gjJ7nv//S/6DfGmsVyD+fbzseaCmKnP41hKNLRDIPGAEnjXWKzUgF4cM89hTpEvWA7+bj2w+ax2ImI5UCarXCX9Q2bjLKkFt6tIaE9YQLIovQtm0qlVTPzHL5cmyZT0MYMROhPZOkicTR/FufvXdkWnrp8Z+rRkOWzGEotNz6f04KEt0I+P1TOHxbbDbSmEZ0Vo4ZeXH5k0xsIlmSdWXOP6cJxp7ym9XSavXy5hwj2rcSC6rokikRM6ryRncWarrKr/UaHcK9mohAn0ferbzPcKSmc1awg2D0c4/MuhtK5yte8ZiW1ijt1QVVC1xd7nxJTCyl50MyJtjbQMy3yBWRiRSrYrcwotPWsrDwdUXT+ooJ7gAfXkoSQbCetcuzFmZE7az3qn+2xXUyt3bikHU= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 88e1b277-ffd3-4b79-99e6-08db0ff2ea20 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2023 07:53:38.9908 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: f5CX7C2kuTcwRJ7sChFFRTmPDhqJpO9fBLCXJ/AZQH0C+RbPv6hAUWlAF/TpUlaM1oIX922a3Hh5ObPcN8aklpFq3rDJ9fo/VPaYs0OmqbE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR10MB5993 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230215_235344_719179_C62A97CF X-CRM114-Status: GOOD ( 12.76 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Ocelot chips have an internal PLL that must be used when communicating through external phys. Expose the init routine, so it can be used by other drivers. Signed-off-by: Colin Foster --- drivers/net/ethernet/mscc/ocelot.c | 31 ++++++++++++++++++++++ drivers/net/ethernet/mscc/ocelot_vsc7514.c | 30 --------------------- include/soc/mscc/ocelot.h | 2 ++ 3 files changed, 33 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c index 08acb7b89086..9b8403e29445 100644 --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "ocelot.h" #include "ocelot_vcap.h" @@ -211,6 +212,36 @@ static void ocelot_mact_init(struct ocelot *ocelot) ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); } +void ocelot_pll5_init(struct ocelot *ocelot) +{ + /* Configure PLL5. This will need a proper CCF driver + * The values are coming from the VTSS API for Ocelot + */ + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, + HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | + HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, + HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | + HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | + HSIO_PLL5G_CFG0_ENA_BIAS | + HSIO_PLL5G_CFG0_ENA_VCO_BUF | + HSIO_PLL5G_CFG0_ENA_CP1 | + HSIO_PLL5G_CFG0_SELCPI(2) | + HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | + HSIO_PLL5G_CFG0_SELBGV820(4) | + HSIO_PLL5G_CFG0_DIV4 | + HSIO_PLL5G_CFG0_ENA_CLKTREE | + HSIO_PLL5G_CFG0_ENA_LANE); + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, + HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | + HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | + HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | + HSIO_PLL5G_CFG2_ENA_AMPCTRL | + HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | + HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); +} +EXPORT_SYMBOL(ocelot_pll5_init); + static void ocelot_vcap_enable(struct ocelot *ocelot, int port) { ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c index 7388c3b0535c..97e90e2869d4 100644 --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c @@ -18,7 +18,6 @@ #include #include -#include #include #include "ocelot_fdma.h" #include "ocelot.h" @@ -26,35 +25,6 @@ #define VSC7514_VCAP_POLICER_BASE 128 #define VSC7514_VCAP_POLICER_MAX 191 -static void ocelot_pll5_init(struct ocelot *ocelot) -{ - /* Configure PLL5. This will need a proper CCF driver - * The values are coming from the VTSS API for Ocelot - */ - regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, - HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | - HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); - regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, - HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | - HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | - HSIO_PLL5G_CFG0_ENA_BIAS | - HSIO_PLL5G_CFG0_ENA_VCO_BUF | - HSIO_PLL5G_CFG0_ENA_CP1 | - HSIO_PLL5G_CFG0_SELCPI(2) | - HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | - HSIO_PLL5G_CFG0_SELBGV820(4) | - HSIO_PLL5G_CFG0_DIV4 | - HSIO_PLL5G_CFG0_ENA_CLKTREE | - HSIO_PLL5G_CFG0_ENA_LANE); - regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, - HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | - HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | - HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | - HSIO_PLL5G_CFG2_ENA_AMPCTRL | - HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | - HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); -} - static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) { int ret; diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 2080879e4134..751d9b250615 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -1183,4 +1183,6 @@ ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, } #endif +void ocelot_pll5_init(struct ocelot *ocelot); + #endif