| Message ID | 20230315100421.133428-2-changhuang.liang@starfivetech.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add JH7110 MIPI DPHY RX support | expand |
On Wed, Mar 15, 2023 at 03:04:19AM -0700, Changhuang Liang wrote: > StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on > a M31 IP. Add a binding for it. > > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> > --- > .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 77 +++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > > diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > new file mode 100644 > index 000000000000..b72ac44bc29d > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive SoC MIPI D-PHY Rx Controller > + > +maintainers: > + - Jack Zhu <jack.zhu@starfivetech.com> > + - Changhuang Liang <changhuang.liang@starfivetech.com> > + > +description: > + The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer > + CSI camera data. > + > +properties: > + compatible: > + const: starfive,jh7110-dphy-rx > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: config clock > + - description: reference clock > + - description: escape mode transmit clock > + > + clock-names: > + items: > + - const: cfg > + - const: ref > + - const: tx > + > + resets: > + items: > + - description: DPHY_HW reset > + - description: DPHY_B09_ALWAYS_ON reset > + > + starfive,aon-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle of AON SYSCON > + - description: register offset > + description: The power of dphy rx is configured by AON SYSCON > + in this property. Sounds like AON SYSCON should be a power-domains provider. Custom phandle links are for things which don't fit standard bindings. > + > + "#phy-cells": > + const: 0 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - resets > + - starfive,aon-syscon > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + phy@19820000 { > + compatible = "starfive,jh7110-dphy-rx"; > + reg = <0x19820000 0x10000>; > + clocks = <&ispcrg 3>, > + <&ispcrg 4>, > + <&ispcrg 5>; > + clock-names = "cfg", "ref", "tx"; > + resets = <&ispcrg 2>, > + <&ispcrg 3>; > + starfive,aon-syscon = <&aon_syscon 0x00>; > + #phy-cells = <0>; > + }; > -- > 2.25.1 >
On 2023/3/20 23:14, Rob Herring wrote: > On Wed, Mar 15, 2023 at 03:04:19AM -0700, Changhuang Liang wrote: >> [...] >> + resets: >> + items: >> + - description: DPHY_HW reset >> + - description: DPHY_B09_ALWAYS_ON reset >> + >> + starfive,aon-syscon: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + items: >> + - items: >> + - description: phandle of AON SYSCON >> + - description: register offset >> + description: The power of dphy rx is configured by AON SYSCON >> + in this property. > > Sounds like AON SYSCON should be a power-domains provider. Custom > phandle links are for things which don't fit standard bindings. > Hi, Rob In starfive jh7110 SoC，we have achieved the power-domains provider as follow: https://patchwork.kernel.org/project/linux-pm/cover/20230119094447.21939-1-walker.chen@starfivetech.com/ But this AON SYSCON is a miscellaneous register. It different offsets configure the different functions of the different modules. So we don't make a framework fot it. What do you think? Thanks >> + >> + "#phy-cells": >> + const: 0 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - resets >> + - starfive,aon-syscon >> + - "#phy-cells" >> [...] >>
On 2023/3/20 23:14, Rob Herring wrote: > On Wed, Mar 15, 2023 at 03:04:19AM -0700, Changhuang Liang wrote: >> StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on >> a M31 IP. Add a binding for it. >> >> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> >> --- >> .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 77 +++++++++++++++++++ >> 1 file changed, 77 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml >> new file mode 100644 >> index 000000000000..b72ac44bc29d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml >> @@ -0,0 +1,77 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: StarFive SoC MIPI D-PHY Rx Controller >> + >> +maintainers: >> + - Jack Zhu <jack.zhu@starfivetech.com> >> + - Changhuang Liang <changhuang.liang@starfivetech.com> >> + >> +description: >> + The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer >> + CSI camera data. >> + >> +properties: >> + compatible: >> + const: starfive,jh7110-dphy-rx >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: config clock >> + - description: reference clock >> + - description: escape mode transmit clock >> + >> + clock-names: >> + items: >> + - const: cfg >> + - const: ref >> + - const: tx >> + >> + resets: >> + items: >> + - description: DPHY_HW reset >> + - description: DPHY_B09_ALWAYS_ON reset >> + >> + starfive,aon-syscon: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + items: >> + - items: >> + - description: phandle of AON SYSCON >> + - description: register offset >> + description: The power of dphy rx is configured by AON SYSCON >> + in this property. > > Sounds like AON SYSCON should be a power-domains provider. Custom > phandle links are for things which don't fit standard bindings. > Hi, Rob, On visionfive2 jh7110 SoC, this AON SYSCON is the Secondary power switch to the DPHY Rx. When we open the pmic switch, we also need to configure the AON SYSCON register to turn on the switch, it is used to link the pmic and the DPHY Rx, So I think it just use syscon framework is enought. What about your comments. I am looking forward to your reply. thanks, >> + >> + "#phy-cells": >> + const: 0 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - resets >> + - starfive,aon-syscon >> + - "#phy-cells" >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + phy@19820000 { >> + compatible = "starfive,jh7110-dphy-rx"; >> + reg = <0x19820000 0x10000>; >> + clocks = <&ispcrg 3>, >> + <&ispcrg 4>, >> + <&ispcrg 5>; >> + clock-names = "cfg", "ref", "tx"; >> + resets = <&ispcrg 2>, >> + <&ispcrg 3>; >> + starfive,aon-syscon = <&aon_syscon 0x00>; >> + #phy-cells = <0>; >> + }; >> -- >> 2.25.1 >>
On 07/04/2023 08:51, Changhuang Liang wrote: >>> + >>> + resets: >>> + items: >>> + - description: DPHY_HW reset >>> + - description: DPHY_B09_ALWAYS_ON reset >>> + >>> + starfive,aon-syscon: >>> + $ref: /schemas/types.yaml#/definitions/phandle-array >>> + items: >>> + - items: >>> + - description: phandle of AON SYSCON >>> + - description: register offset >>> + description: The power of dphy rx is configured by AON SYSCON >>> + in this property. >> >> Sounds like AON SYSCON should be a power-domains provider. Custom >> phandle links are for things which don't fit standard bindings. >> > > Hi, Rob, > > On visionfive2 jh7110 SoC, this AON SYSCON is the Secondary power switch to the DPHY Rx. > When we open the pmic switch, we also need to configure the AON SYSCON register to turn > on the switch, it is used to link the pmic and the DPHY Rx, So I think it just use syscon > framework is enought. What about your comments. Which sounds exactly like power domain provider... Best regards, Krzysztof
On 2023/4/7 14:54, Krzysztof Kozlowski wrote: > On 07/04/2023 08:51, Changhuang Liang wrote: >>>> + >>>> + resets: >>>> + items: >>>> + - description: DPHY_HW reset >>>> + - description: DPHY_B09_ALWAYS_ON reset >>>> + >>>> + starfive,aon-syscon: >>>> + $ref: /schemas/types.yaml#/definitions/phandle-array >>>> + items: >>>> + - items: >>>> + - description: phandle of AON SYSCON >>>> + - description: register offset >>>> + description: The power of dphy rx is configured by AON SYSCON >>>> + in this property. >>> >>> Sounds like AON SYSCON should be a power-domains provider. Custom >>> phandle links are for things which don't fit standard bindings. >>> >> >> Hi, Rob, >> >> On visionfive2 jh7110 SoC, this AON SYSCON is the Secondary power switch to the DPHY Rx. >> When we open the pmic switch, we also need to configure the AON SYSCON register to turn >> on the switch, it is used to link the pmic and the DPHY Rx, So I think it just use syscon >> framework is enought. What about your comments. > > Which sounds exactly like power domain provider... > OK, thanks for your comment, I will try to use power domain framework in next patch. > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml new file mode 100644 index 000000000000..b72ac44bc29d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive SoC MIPI D-PHY Rx Controller + +maintainers: + - Jack Zhu <jack.zhu@starfivetech.com> + - Changhuang Liang <changhuang.liang@starfivetech.com> + +description: + The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer + CSI camera data. + +properties: + compatible: + const: starfive,jh7110-dphy-rx + + reg: + maxItems: 1 + + clocks: + items: + - description: config clock + - description: reference clock + - description: escape mode transmit clock + + clock-names: + items: + - const: cfg + - const: ref + - const: tx + + resets: + items: + - description: DPHY_HW reset + - description: DPHY_B09_ALWAYS_ON reset + + starfive,aon-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of AON SYSCON + - description: register offset + description: The power of dphy rx is configured by AON SYSCON + in this property. + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - starfive,aon-syscon + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@19820000 { + compatible = "starfive,jh7110-dphy-rx"; + reg = <0x19820000 0x10000>; + clocks = <&ispcrg 3>, + <&ispcrg 4>, + <&ispcrg 5>; + clock-names = "cfg", "ref", "tx"; + resets = <&ispcrg 2>, + <&ispcrg 3>; + starfive,aon-syscon = <&aon_syscon 0x00>; + #phy-cells = <0>; + };
StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on a M31 IP. Add a binding for it. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> --- .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml