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Miller" , Florian Fainelli , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [PATCH v2 net-next 3/9] net: mscc: ocelot: expose ocelot_pll5_init routine Date: Fri, 17 Mar 2023 11:54:09 -0700 Message-Id: <20230317185415.2000564-4-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230317185415.2000564-1-colin.foster@in-advantage.com> References: <20230317185415.2000564-1-colin.foster@in-advantage.com> X-ClientProxiedBy: BY5PR16CA0025.namprd16.prod.outlook.com (2603:10b6:a03:1a0::38) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWHPR1001MB2351:EE_|MN0PR10MB5959:EE_ X-MS-Office365-Filtering-Correlation-Id: aa1bf46f-04ba-489e-6216-08db27190bb4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qPIGR7sGnv4hu8P7DX4E0Rizxj2zA8nMIYyOVdVC1W8I645IW20qSvu/yep6f8+YtQqJX3YcdAuxdkctRFJXe45O9wvI3f4YQ84vYd6R6DTbGWAgRhyd1A7D1Wfpag0K8IqZfIy93YSk7s6QSQWdmsCK3p0JHboh8bTB0dPTGDKn4msvH5DH8yoquouqo1iOKfnbRjlRb6kn+7HguUlJwKBkUwdG7lu+iuHSCl4kwxkrDOQBXc01fP2riSL3UGjJkx/F0LNhqCjgLHNm20ST8/pZVAdFtp0xhNlK1GT6m7fUl68KJkl/uvsuod+c0mWHyEq66zfBzgjaY86Qvt0LQQSg5vLT20t8CSwmqqoAwa+oitAe2M7YD021LyxUAUPcJRHdZwh+PWHpwmLqqJLblscvPdPwmgkV17/P7/8w/y/kv12JxsVZner5kd+l6dPf9IAQzzCilXI3cpZQdhUdTldEsAmsz6U34Ega/ligfhpoDlCWoemi0q0jnfUjzFRTjDbzQAiaVe4sxfSYq2X/6Mu6KJ+E4FRXxQ4a4LNuXD+s5Ef0zB8kVawyuruj2QleVQu8COSEEu4JqJRsMHYCD6rZ/yEPwXOMUS49E6vzo9okrrqslEqCF8/IdvCe2UCb68ZhkK6AvHFJ3WYmRfacRYqd+TuC4KhzR4HxSGaJtW8frrovo70PsLs53eucxaztxiqX/xJsKvAbCV/TFCc6Ew== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(396003)(346002)(376002)(39830400003)(136003)(366004)(451199018)(8676002)(86362001)(5660300002)(44832011)(7416002)(478600001)(66946007)(66556008)(2616005)(52116002)(186003)(38350700002)(6486002)(6666004)(2906002)(6512007)(1076003)(6506007)(26005)(36756003)(66476007)(38100700002)(316002)(41300700001)(54906003)(8936002)(83380400001)(4326008);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xIdDDfeuHyMQIH9BXjCrnAirGmjeErLZ8rv9h4WFDqhzDcbCs6NEqhF2xscFl80SifhJ0FggGn9joKsJbXFL4fse0kUCRGi4pwFTYr3pGCBcE3SoXuONMsZB5E4TLZwrWVWao7p/Ixl71VZ8QEw4Ks97Fktse/FI1CRKJ6NQg4Nziq2TwDzeeAApniCYg4PFNeo8Yu7yQP34xD5l7aK9sG1oymnS9TLTVfLXHDpfqXKp10BksyJVoP/f42JJSAB5QNu2dnAEmXA22Sgg5gOnC10fU5OPLDgyhfasUH1hDS9nuDwSnS3O+HFiO/uqMNiADrFMGCdyOMDUQFbntwPv6cxmyCQaJ1Brzoyo7vbW3eU4fSYILdEkSevnu9z6IIQX+94Kxb8y+OqORHgr8+nbwdN0fXYm9L2vDQtRYuZ98HpMYfLkpuNU+KAilyHOv7g+enL442q5o5/ZzpHgGNA6y6zm/SVxKt6+MeU87q4MD0ZwpFdYqXQaWi5QGmgX6qUL7MEz2rc0iDBqlLrQZg1+MOQIocSpEm3pU5IOMiYpPZMtRaqT1zvsTBP+ykU0WYK2YlyHwUPYJwanlOJllAtBbHkQ21hRfcrhQ4pbOUKpUbxp4f7eoCanE+nls79T36A94zbDuuU4ZmcAGjqe80L48vMKgDrv62FZ6e9/SOyCVOXmwXz0UPup0O8moil1tOoc5yHGAAMs7uATZB/reA0rwwTxhfn4Eh2GDEeWKOhQp1sHTQuNSZravPA+Ny7/zxF3P5M4NkcSy6shwJ5RwXq4NZpXZYyw4PGsaXTYCcXdhgPjXg6nNu7/58ZALVs6bEl3rLnfkvwNEDOxf5GP+gsOTyIgVYfvN+AkMYgjWNFqM21UVcFKb6NaOM+Frg275jbDyF87Pp6gndOKheWBFhnONMK9KgWg2kLpXkuUAcq4cmGTcIUyNGbhPmeFM+zoMSPeq/5mdBaUqy8Q2mvuZ1PM1t3YtNv2+Z0xyd1oxUlNgM8nueS7T3UE5zpr31m2q4H4PIuFFAY5cHo7cbzl74P23neDAZH630hfh3L5DXka1t+cEHq9MPPzummc7R5PMIbmRDJxPDm7yw56ZCj8OrK/ICnRBHlpem44CgWvtILxqpVffKoH1WAGVEb2tAwj2hWwfu9RIAEVrreiLn79ZunfACtXKGyADsvMRX0KBfJ5e+vCnGa8gG+Wf0ESxs8aQQ11aKoCWJMTBvld12s+Jnd1MBNow02wNaX+oTV7c9IpxRK4lVr6eAKSJIcGrK0tKd1D9roPqhcZyzRbHwg7eofBJhcyWFYJi+yQltBT3Z/DXQMzTT/GZDAQuD/3Lk6TWO+jsnG+0CBsAFpOwI6FBON4/GwZzmRxNyLuD1R+rUnjx71VcUZJCodnKtMP8aywGOGjOoVeLcPq3+LcjEp3zItLboa0++Ly3+YRfQsUhhxCkborWQmTwWGW03Ocuxyg0u2A9TVkX8nGIlB0dnlSfQFt2I4C9/9ZC4gzZunEXK+5MXqEBiRguP1vbR4TDwzt/oFUcbTM6x5ScwmrD9RGd4j75Dlu0rmsfeAtccJipV437eviAs/HXM4Xq4hikFII+l8KW6U72h0ZB9EsmQy/ukNdFgPeACAXRI2wfslr2HMm9Xs= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: aa1bf46f-04ba-489e-6216-08db27190bb4 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2023 18:54:32.8968 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Gj6GtdgsWJHWuCw3i5zL9BwhG/a2IL/yK5UH/O7cx9R2X2Z4hTcxxlLFEq1tXnLMPAzlijZkDGO73AQLz5uQ9/yl4b6LFQUMKu5v7q3WAek= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR10MB5959 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230317_115439_959999_D7E07588 X-CRM114-Status: GOOD ( 12.81 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Ocelot chips have an internal PLL that must be used when communicating through external phys. Expose the init routine, so it can be used by other drivers. Signed-off-by: Colin Foster --- v1 -> v2 * No change --- drivers/net/ethernet/mscc/ocelot.c | 31 ++++++++++++++++++++++ drivers/net/ethernet/mscc/ocelot_vsc7514.c | 30 --------------------- include/soc/mscc/ocelot.h | 2 ++ 3 files changed, 33 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c index 08acb7b89086..9b8403e29445 100644 --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "ocelot.h" #include "ocelot_vcap.h" @@ -211,6 +212,36 @@ static void ocelot_mact_init(struct ocelot *ocelot) ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); } +void ocelot_pll5_init(struct ocelot *ocelot) +{ + /* Configure PLL5. This will need a proper CCF driver + * The values are coming from the VTSS API for Ocelot + */ + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, + HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | + HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, + HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | + HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | + HSIO_PLL5G_CFG0_ENA_BIAS | + HSIO_PLL5G_CFG0_ENA_VCO_BUF | + HSIO_PLL5G_CFG0_ENA_CP1 | + HSIO_PLL5G_CFG0_SELCPI(2) | + HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | + HSIO_PLL5G_CFG0_SELBGV820(4) | + HSIO_PLL5G_CFG0_DIV4 | + HSIO_PLL5G_CFG0_ENA_CLKTREE | + HSIO_PLL5G_CFG0_ENA_LANE); + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, + HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | + HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | + HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | + HSIO_PLL5G_CFG2_ENA_AMPCTRL | + HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | + HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); +} +EXPORT_SYMBOL(ocelot_pll5_init); + static void ocelot_vcap_enable(struct ocelot *ocelot, int port) { ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c index 7388c3b0535c..97e90e2869d4 100644 --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c @@ -18,7 +18,6 @@ #include #include -#include #include #include "ocelot_fdma.h" #include "ocelot.h" @@ -26,35 +25,6 @@ #define VSC7514_VCAP_POLICER_BASE 128 #define VSC7514_VCAP_POLICER_MAX 191 -static void ocelot_pll5_init(struct ocelot *ocelot) -{ - /* Configure PLL5. This will need a proper CCF driver - * The values are coming from the VTSS API for Ocelot - */ - regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, - HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | - HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); - regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, - HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | - HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | - HSIO_PLL5G_CFG0_ENA_BIAS | - HSIO_PLL5G_CFG0_ENA_VCO_BUF | - HSIO_PLL5G_CFG0_ENA_CP1 | - HSIO_PLL5G_CFG0_SELCPI(2) | - HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | - HSIO_PLL5G_CFG0_SELBGV820(4) | - HSIO_PLL5G_CFG0_DIV4 | - HSIO_PLL5G_CFG0_ENA_CLKTREE | - HSIO_PLL5G_CFG0_ENA_LANE); - regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, - HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | - HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | - HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | - HSIO_PLL5G_CFG2_ENA_AMPCTRL | - HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | - HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); -} - static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) { int ret; diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 2080879e4134..751d9b250615 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -1183,4 +1183,6 @@ ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, } #endif +void ocelot_pll5_init(struct ocelot *ocelot); + #endif