| Message ID | 20230324022514.1800382-5-dmitry.baryshkov@linaro.org |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | phy: qcom-qmp: convert to newer style of bindings | expand |
On Fri, Mar 24, 2023 at 05:24:37AM +0300, Dmitry Baryshkov wrote: > Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml) > to qcom,sc8280xp-qmp-pcie-phy.yaml. This removes a need to declare > the child PHY node or split resource regions. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 299 ------------------ > .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 213 +++++++++++-- > 2 files changed, 187 insertions(+), 325 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > index ef49efbd0a20..328588448c6b 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > @@ -16,10 +16,23 @@ description: > properties: > compatible: > enum: > + - qcom,ipq6018-qmp-pcie-phy > + - qcom,ipq8074-qmp-gen3-pcie-phy > + - qcom,ipq8074-qmp-pcie-phy > + - qcom,msm8998-qmp-pcie-phy > + - qcom,sc8180x-qmp-pcie-phy > - qcom,sc8280xp-qmp-gen3x1-pcie-phy > - qcom,sc8280xp-qmp-gen3x2-pcie-phy > - qcom,sc8280xp-qmp-gen3x4-pcie-phy > + - qcom,sdm845-qhp-pcie-phy > + - qcom,sdm845-qmp-pcie-phy > + - qcom,sdx55-qmp-pcie-phy > + - qcom,sm8250-qmp-gen3x1-pcie-phy > + - qcom,sm8250-qmp-gen3x2-pcie-phy > + - qcom,sm8250-qmp-modem-pcie-phy > - qcom,sm8350-qmp-gen3x1-pcie-phy > + - qcom,sm8450-qmp-gen3x1-pcie-phy > + - qcom,sm8450-qmp-gen4x2-pcie-phy > - qcom,sm8550-qmp-gen3x2-pcie-phy > - qcom,sm8550-qmp-gen4x2-pcie-phy > > @@ -28,18 +41,12 @@ properties: > maxItems: 2 > > clocks: > - minItems: 5 > + minItems: 3 > maxItems: 6 > > clock-names: > - minItems: 5 > - items: > - - const: aux > - - const: cfg_ahb > - - const: ref > - - const: rchng > - - const: pipe > - - const: pipediv2 > + minItems: 3 > + maxItems: 6 > > power-domains: > maxItems: 1 > @@ -50,9 +57,7 @@ properties: > > reset-names: > minItems: 1 > - items: > - - const: phy > - - const: phy_nocsr > + maxItems: 2 > > vdda-phy-supply: true > > @@ -83,11 +88,8 @@ required: > - reg > - clocks > - clock-names > - - power-domains > - resets > - reset-names > - - vdda-phy-supply > - - vdda-pll-supply > - "#clock-cells" > - clock-output-names > - "#phy-cells" > @@ -119,21 +121,116 @@ allOf: > compatible: > contains: > enum: > - - qcom,sm8350-qmp-gen3x1-pcie-phy > - - qcom,sm8550-qmp-gen3x2-pcie-phy > - - qcom,sm8550-qmp-gen4x2-pcie-phy > + - qcom,msm8998-qmp-pcie-phy > then: > properties: > clocks: > - maxItems: 5 > + maxItems: 4 > clock-names: > + items: > + - const: aux > + - const: cfg_ahb > + - const: ref > + - const: pipe > + resets: > + maxItems: 2 > + reset-names: > + items: > + - const: phy > + - const: common Reset name looks wrong here too. > + required: > + - vdda-phy-supply > + - vdda-pll-supply > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,ipq6018-qmp-pcie-phy > + - qcom,ipq8074-qmp-gen3-pcie-phy > + - qcom,ipq8074-qmp-pcie-phy > + then: > + properties: > + clocks: > + maxItems: 3 > + clock-names: > + items: > + - const: aux > + - const: cfg_ahb > + - const: pipe > + resets: > + maxItems: 2 > + reset-names: > + items: > + - const: phy > + - const: common Same here. > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sc8180x-qmp-pcie-phy > + - qcom,sdm845-qhp-pcie-phy > + - qcom,sdm845-qmp-pcie-phy > + - qcom,sdx55-qmp-pcie-phy > + - qcom,sm8250-qmp-gen3x1-pcie-phy > + - qcom,sm8250-qmp-gen3x2-pcie-phy > + - qcom,sm8250-qmp-modem-pcie-phy > + - qcom,sm8450-qmp-gen3x1-pcie-phy > + - qcom,sm8450-qmp-gen4x2-pcie-phy > + then: > + properties: > + clocks: > maxItems: 5 > - else: > + clock-names: > + items: > + - const: aux > + - const: cfg_ahb > + - const: ref > + - const: refgen This one should be named 'rchng' and this set a strict subset of the sc8280xp clocks. > + - const: pipe > + resets: > + maxItems: 1 > + reset-names: > + items: > + - const: phy > + required: > + - vdda-phy-supply > + - vdda-pll-supply > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sm8350-qmp-gen3x1-pcie-phy > + - qcom,sm8550-qmp-gen3x2-pcie-phy > + resets: > + minItems: 1 > + reset-names: > + items: > + - const: phy > + then: > properties: > clocks: > - minItems: 6 > + maxItems: 5 > clock-names: > - minItems: 6 > + items: > + - const: aux > + - const: cfg_ahb > + - const: ref > + - const: rchng > + - const: pipe > + resets: > + maxItems: 1 > + reset-names: > + items: > + - const: phy > + required: > + - vdda-phy-supply > + - vdda-pll-supply > > - if: > properties: > @@ -143,16 +240,53 @@ allOf: > - qcom,sm8550-qmp-gen4x2-pcie-phy > then: > properties: > + clocks: > + maxItems: 5 > + clock-names: > + items: > + - const: aux > + - const: cfg_ahb > + - const: ref > + - const: rchng > + - const: pipe > resets: > minItems: 2 > reset-names: > - minItems: 2 > - else: > + items: > + - const: phy > + - const: phy_nocsr > + required: > + - vdda-phy-supply > + - vdda-pll-supply > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sc8280xp-qmp-gen3x1-pcie-phy > + - qcom,sc8280xp-qmp-gen3x2-pcie-phy > + - qcom,sc8280xp-qmp-gen3x4-pcie-phy > + then: > properties: > + clocks: > + minItems: 6 > + clock-names: > + items: > + - const: aux > + - const: cfg_ahb > + - const: ref > + - const: rchng > + - const: pipe > + - const: pipediv2 > resets: > - maxItems: 1 > + minItems: 1 > reset-names: > - maxItems: 1 > + items: > + - const: phy > + required: > + - vdda-phy-supply > + - vdda-pll-supply > > examples: > - | > @@ -213,3 +347,30 @@ examples: > > #phy-cells = <0>; > }; > + - | > + #define GCC_PCIE1_PHY_REFGEN_CLK 47 > + #define GCC_PCIE_PHY_AUX_CLK 71 > + #define GCC_PCIE_WIGIG_CLKREF_EN 74 > + > + phy@1c0e000 { > + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; > + reg = <0x01c0e000 0x1c0>; > + > + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, > + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, > + <&gcc GCC_PCIE_1_PIPE_CLK>; > + clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe"; > + > + resets = <&gcc GCC_PCIE_1_PHY_BCR>; > + reset-names = "phy"; > + > + vdda-phy-supply = <&vreg_l10c_0p88>; > + vdda-pll-supply = <&vreg_l6b_1p2>; > + > + #clock-cells = <0>; > + clock-output-names = "pcie_1_pipe_clk"; > + > + #phy-cells = <0>; > + }; This example also looks redundant. Johan
On Fri, 24 Mar 2023 at 10:04, Johan Hovold <johan@kernel.org> wrote: > > On Fri, Mar 24, 2023 at 05:24:37AM +0300, Dmitry Baryshkov wrote: > > Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml) > > to qcom,sc8280xp-qmp-pcie-phy.yaml. This removes a need to declare > > the child PHY node or split resource regions. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 299 ------------------ > > .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 213 +++++++++++-- > > 2 files changed, 187 insertions(+), 325 deletions(-) > > delete mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml > > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > > index ef49efbd0a20..328588448c6b 100644 > > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > > @@ -16,10 +16,23 @@ description: > > properties: > > compatible: > > enum: > > + - qcom,ipq6018-qmp-pcie-phy > > + - qcom,ipq8074-qmp-gen3-pcie-phy > > + - qcom,ipq8074-qmp-pcie-phy > > + - qcom,msm8998-qmp-pcie-phy > > + - qcom,sc8180x-qmp-pcie-phy > > - qcom,sc8280xp-qmp-gen3x1-pcie-phy > > - qcom,sc8280xp-qmp-gen3x2-pcie-phy > > - qcom,sc8280xp-qmp-gen3x4-pcie-phy > > + - qcom,sdm845-qhp-pcie-phy > > + - qcom,sdm845-qmp-pcie-phy > > + - qcom,sdx55-qmp-pcie-phy > > + - qcom,sm8250-qmp-gen3x1-pcie-phy > > + - qcom,sm8250-qmp-gen3x2-pcie-phy > > + - qcom,sm8250-qmp-modem-pcie-phy > > - qcom,sm8350-qmp-gen3x1-pcie-phy > > + - qcom,sm8450-qmp-gen3x1-pcie-phy > > + - qcom,sm8450-qmp-gen4x2-pcie-phy > > - qcom,sm8550-qmp-gen3x2-pcie-phy > > - qcom,sm8550-qmp-gen4x2-pcie-phy > > > > @@ -28,18 +41,12 @@ properties: > > maxItems: 2 > > > > clocks: > > - minItems: 5 > > + minItems: 3 > > maxItems: 6 > > > > clock-names: > > - minItems: 5 > > - items: > > - - const: aux > > - - const: cfg_ahb > > - - const: ref > > - - const: rchng > > - - const: pipe > > - - const: pipediv2 > > + minItems: 3 > > + maxItems: 6 > > > > power-domains: > > maxItems: 1 > > @@ -50,9 +57,7 @@ properties: > > > > reset-names: > > minItems: 1 > > - items: > > - - const: phy > > - - const: phy_nocsr > > + maxItems: 2 > > > > vdda-phy-supply: true > > > > @@ -83,11 +88,8 @@ required: > > - reg > > - clocks > > - clock-names > > - - power-domains > > - resets > > - reset-names > > - - vdda-phy-supply > > - - vdda-pll-supply > > - "#clock-cells" > > - clock-output-names > > - "#phy-cells" > > @@ -119,21 +121,116 @@ allOf: > > compatible: > > contains: > > enum: > > - - qcom,sm8350-qmp-gen3x1-pcie-phy > > - - qcom,sm8550-qmp-gen3x2-pcie-phy > > - - qcom,sm8550-qmp-gen4x2-pcie-phy > > + - qcom,msm8998-qmp-pcie-phy > > then: > > properties: > > clocks: > > - maxItems: 5 > > + maxItems: 4 > > clock-names: > > + items: > > + - const: aux > > + - const: cfg_ahb > > + - const: ref > > + - const: pipe > > + resets: > > + maxItems: 2 > > + reset-names: > > + items: > > + - const: phy > > + - const: common > > Reset name looks wrong here too. > > > + required: > > + - vdda-phy-supply > > + - vdda-pll-supply > > + > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - qcom,ipq6018-qmp-pcie-phy > > + - qcom,ipq8074-qmp-gen3-pcie-phy > > + - qcom,ipq8074-qmp-pcie-phy > > + then: > > + properties: > > + clocks: > > + maxItems: 3 > > + clock-names: > > + items: > > + - const: aux > > + - const: cfg_ahb > > + - const: pipe > > + resets: > > + maxItems: 2 > > + reset-names: > > + items: > > + - const: phy > > + - const: common > > Same here. > > > + > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - qcom,sc8180x-qmp-pcie-phy > > + - qcom,sdm845-qhp-pcie-phy > > + - qcom,sdm845-qmp-pcie-phy > > + - qcom,sdx55-qmp-pcie-phy > > + - qcom,sm8250-qmp-gen3x1-pcie-phy > > + - qcom,sm8250-qmp-gen3x2-pcie-phy > > + - qcom,sm8250-qmp-modem-pcie-phy > > + - qcom,sm8450-qmp-gen3x1-pcie-phy > > + - qcom,sm8450-qmp-gen4x2-pcie-phy > > + then: > > + properties: > > + clocks: > > maxItems: 5 > > - else: > > + clock-names: > > + items: > > + - const: aux > > + - const: cfg_ahb > > + - const: ref > > + - const: refgen > > This one should be named 'rchng' and this set a strict subset of the > sc8280xp clocks. Ack. Same story as the resets. Let's stop my grumbling and move clock/reset parsing to legacy vs non-legacy code. > > > + - const: pipe > > + resets: > > + maxItems: 1 > > + reset-names: > > + items: > > + - const: phy > > + required: > > + - vdda-phy-supply > > + - vdda-pll-supply > > + > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - qcom,sm8350-qmp-gen3x1-pcie-phy > > + - qcom,sm8550-qmp-gen3x2-pcie-phy > > + resets: > > + minItems: 1 > > + reset-names: > > + items: > > + - const: phy > > + then: > > properties: > > clocks: > > - minItems: 6 > > + maxItems: 5 > > clock-names: > > - minItems: 6 > > + items: > > + - const: aux > > + - const: cfg_ahb > > + - const: ref > > + - const: rchng > > + - const: pipe > > + resets: > > + maxItems: 1 > > + reset-names: > > + items: > > + - const: phy > > + required: > > + - vdda-phy-supply > > + - vdda-pll-supply > > > > - if: > > properties: > > @@ -143,16 +240,53 @@ allOf: > > - qcom,sm8550-qmp-gen4x2-pcie-phy > > then: > > properties: > > + clocks: > > + maxItems: 5 > > + clock-names: > > + items: > > + - const: aux > > + - const: cfg_ahb > > + - const: ref > > + - const: rchng > > + - const: pipe > > resets: > > minItems: 2 > > reset-names: > > - minItems: 2 > > - else: > > + items: > > + - const: phy > > + - const: phy_nocsr > > + required: > > + - vdda-phy-supply > > + - vdda-pll-supply > > + > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - qcom,sc8280xp-qmp-gen3x1-pcie-phy > > + - qcom,sc8280xp-qmp-gen3x2-pcie-phy > > + - qcom,sc8280xp-qmp-gen3x4-pcie-phy > > + then: > > properties: > > + clocks: > > + minItems: 6 > > + clock-names: > > + items: > > + - const: aux > > + - const: cfg_ahb > > + - const: ref > > + - const: rchng > > + - const: pipe > > + - const: pipediv2 > > resets: > > - maxItems: 1 > > + minItems: 1 > > reset-names: > > - maxItems: 1 > > + items: > > + - const: phy > > + required: > > + - vdda-phy-supply > > + - vdda-pll-supply > > > > examples: > > - | > > @@ -213,3 +347,30 @@ examples: > > > > #phy-cells = <0>; > > }; > > + - | > > + #define GCC_PCIE1_PHY_REFGEN_CLK 47 > > + #define GCC_PCIE_PHY_AUX_CLK 71 > > + #define GCC_PCIE_WIGIG_CLKREF_EN 74 > > + > > + phy@1c0e000 { > > + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; > > + reg = <0x01c0e000 0x1c0>; > > + > > + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, > > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, > > + <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, > > + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, > > + <&gcc GCC_PCIE_1_PIPE_CLK>; > > + clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe"; > > + > > + resets = <&gcc GCC_PCIE_1_PHY_BCR>; > > + reset-names = "phy"; > > + > > + vdda-phy-supply = <&vreg_l10c_0p88>; > > + vdda-pll-supply = <&vreg_l6b_1p2>; > > + > > + #clock-cells = <0>; > > + clock-output-names = "pcie_1_pipe_clk"; > > + > > + #phy-cells = <0>; > > + }; > > This example also looks redundant. > > Johan
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml deleted file mode 100644 index 62045dcfb20c..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml +++ /dev/null @@ -1,299 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm QMP PHY controller (PCIe, IPQ8074) - -maintainers: - - Vinod Koul <vkoul@kernel.org> - -description: - QMP PHY controller supports physical layer functionality for a number of - controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. - - Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see - qcom,sc8280xp-qmp-pcie-phy.yaml. - -properties: - compatible: - enum: - - qcom,ipq6018-qmp-pcie-phy - - qcom,ipq8074-qmp-gen3-pcie-phy - - qcom,ipq8074-qmp-pcie-phy - - qcom,msm8998-qmp-pcie-phy - - qcom,sc8180x-qmp-pcie-phy - - qcom,sdm845-qhp-pcie-phy - - qcom,sdm845-qmp-pcie-phy - - qcom,sdx55-qmp-pcie-phy - - qcom,sm8250-qmp-gen3x1-pcie-phy - - qcom,sm8250-qmp-gen3x2-pcie-phy - - qcom,sm8250-qmp-modem-pcie-phy - - qcom,sm8450-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen4x2-pcie-phy - - reg: - items: - - description: serdes - - "#address-cells": - enum: [ 1, 2 ] - - "#size-cells": - enum: [ 1, 2 ] - - ranges: true - - clocks: - minItems: 2 - maxItems: 4 - - clock-names: - minItems: 2 - maxItems: 4 - - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - vdda-phy-supply: true - - vdda-pll-supply: true - - vddp-ref-clk-supply: true - -patternProperties: - "^phy@[0-9a-f]+$": - type: object - description: single PHY-provider child node - properties: - reg: - minItems: 3 - maxItems: 6 - - clocks: - items: - - description: PIPE clock - - clock-names: - deprecated: true - items: - - const: pipe0 - - "#clock-cells": - const: 0 - - clock-output-names: - maxItems: 1 - - "#phy-cells": - const: 0 - - required: - - reg - - clocks - - "#clock-cells" - - clock-output-names - - "#phy-cells" - - additionalProperties: false - -required: - - compatible - - reg - - "#address-cells" - - "#size-cells" - - ranges - - clocks - - clock-names - - resets - - reset-names - -additionalProperties: false - -allOf: - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8998-qmp-pcie-phy - then: - properties: - clocks: - maxItems: 3 - clock-names: - items: - - const: aux - - const: cfg_ahb - - const: ref - resets: - maxItems: 2 - reset-names: - items: - - const: phy - - const: common - required: - - vdda-phy-supply - - vdda-pll-supply - - - if: - properties: - compatible: - contains: - enum: - - qcom,ipq6018-qmp-pcie-phy - - qcom,ipq8074-qmp-gen3-pcie-phy - - qcom,ipq8074-qmp-pcie-phy - then: - properties: - clocks: - maxItems: 2 - clock-names: - items: - - const: aux - - const: cfg_ahb - resets: - maxItems: 2 - reset-names: - items: - - const: phy - - const: common - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc8180x-qmp-pcie-phy - - qcom,sdm845-qhp-pcie-phy - - qcom,sdm845-qmp-pcie-phy - - qcom,sdx55-qmp-pcie-phy - - qcom,sm8250-qmp-gen3x1-pcie-phy - - qcom,sm8250-qmp-gen3x2-pcie-phy - - qcom,sm8250-qmp-modem-pcie-phy - - qcom,sm8450-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen4x2-pcie-phy - then: - properties: - clocks: - maxItems: 4 - clock-names: - items: - - const: aux - - const: cfg_ahb - - const: ref - - const: refgen - resets: - maxItems: 1 - reset-names: - items: - - const: phy - required: - - vdda-phy-supply - - vdda-pll-supply - - - if: - properties: - compatible: - contains: - enum: - - qcom,sm8250-qmp-gen3x2-pcie-phy - - qcom,sm8250-qmp-modem-pcie-phy - - qcom,sm8450-qmp-gen4x2-pcie-phy - then: - patternProperties: - "^phy@[0-9a-f]+$": - properties: - reg: - items: - - description: TX lane 1 - - description: RX lane 1 - - description: PCS - - description: TX lane 2 - - description: RX lane 2 - - description: PCS_MISC - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc8180x-qmp-pcie-phy - - qcom,sdm845-qmp-pcie-phy - - qcom,sdx55-qmp-pcie-phy - - qcom,sm8250-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen3x1-pcie-phy - then: - patternProperties: - "^phy@[0-9a-f]+$": - properties: - reg: - items: - - description: TX - - description: RX - - description: PCS - - description: PCS_MISC - - - if: - properties: - compatible: - contains: - enum: - - qcom,ipq6018-qmp-pcie-phy - - qcom,ipq8074-qmp-pcie-phy - - qcom,msm8998-qmp-pcie-phy - - qcom,sdm845-qhp-pcie-phy - then: - patternProperties: - "^phy@[0-9a-f]+$": - properties: - reg: - items: - - description: TX - - description: RX - - description: PCS - -examples: - - | - #include <dt-bindings/clock/qcom,gcc-sm8250.h> - phy-wrapper@1c0e000 { - compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; - reg = <0x01c0e000 0x1c0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x01c0e000 0x1000>; - - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, - <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "phy"; - - vdda-phy-supply = <&vreg_l10c_0p88>; - vdda-pll-supply = <&vreg_l6b_1p2>; - - phy@200 { - reg = <0x200 0x170>, - <0x400 0x200>, - <0xa00 0x1f0>, - <0x600 0x170>, - <0x800 0x200>, - <0xe00 0xf4>; - - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - - #clock-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - - #phy-cells = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index ef49efbd0a20..328588448c6b 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -16,10 +16,23 @@ description: properties: compatible: enum: + - qcom,ipq6018-qmp-pcie-phy + - qcom,ipq8074-qmp-gen3-pcie-phy + - qcom,ipq8074-qmp-pcie-phy + - qcom,msm8998-qmp-pcie-phy + - qcom,sc8180x-qmp-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + - qcom,sdx55-qmp-pcie-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen4x2-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy @@ -28,18 +41,12 @@ properties: maxItems: 2 clocks: - minItems: 5 + minItems: 3 maxItems: 6 clock-names: - minItems: 5 - items: - - const: aux - - const: cfg_ahb - - const: ref - - const: rchng - - const: pipe - - const: pipediv2 + minItems: 3 + maxItems: 6 power-domains: maxItems: 1 @@ -50,9 +57,7 @@ properties: reset-names: minItems: 1 - items: - - const: phy - - const: phy_nocsr + maxItems: 2 vdda-phy-supply: true @@ -83,11 +88,8 @@ required: - reg - clocks - clock-names - - power-domains - resets - reset-names - - vdda-phy-supply - - vdda-pll-supply - "#clock-cells" - clock-output-names - "#phy-cells" @@ -119,21 +121,116 @@ allOf: compatible: contains: enum: - - qcom,sm8350-qmp-gen3x1-pcie-phy - - qcom,sm8550-qmp-gen3x2-pcie-phy - - qcom,sm8550-qmp-gen4x2-pcie-phy + - qcom,msm8998-qmp-pcie-phy then: properties: clocks: - maxItems: 5 + maxItems: 4 clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: pipe + resets: + maxItems: 2 + reset-names: + items: + - const: phy + - const: common + required: + - vdda-phy-supply + - vdda-pll-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq6018-qmp-pcie-phy + - qcom,ipq8074-qmp-gen3-pcie-phy + - qcom,ipq8074-qmp-pcie-phy + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: pipe + resets: + maxItems: 2 + reset-names: + items: + - const: phy + - const: common + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-qmp-pcie-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + - qcom,sdx55-qmp-pcie-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen4x2-pcie-phy + then: + properties: + clocks: maxItems: 5 - else: + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: refgen + - const: pipe + resets: + maxItems: 1 + reset-names: + items: + - const: phy + required: + - vdda-phy-supply + - vdda-pll-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8550-qmp-gen3x2-pcie-phy + resets: + minItems: 1 + reset-names: + items: + - const: phy + then: properties: clocks: - minItems: 6 + maxItems: 5 clock-names: - minItems: 6 + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe + resets: + maxItems: 1 + reset-names: + items: + - const: phy + required: + - vdda-phy-supply + - vdda-pll-supply - if: properties: @@ -143,16 +240,53 @@ allOf: - qcom,sm8550-qmp-gen4x2-pcie-phy then: properties: + clocks: + maxItems: 5 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe resets: minItems: 2 reset-names: - minItems: 2 - else: + items: + - const: phy + - const: phy_nocsr + required: + - vdda-phy-supply + - vdda-pll-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-qmp-gen3x1-pcie-phy + - qcom,sc8280xp-qmp-gen3x2-pcie-phy + - qcom,sc8280xp-qmp-gen3x4-pcie-phy + then: properties: + clocks: + minItems: 6 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe + - const: pipediv2 resets: - maxItems: 1 + minItems: 1 reset-names: - maxItems: 1 + items: + - const: phy + required: + - vdda-phy-supply + - vdda-pll-supply examples: - | @@ -213,3 +347,30 @@ examples: #phy-cells = <0>; }; + - | + #define GCC_PCIE1_PHY_REFGEN_CLK 47 + #define GCC_PCIE_PHY_AUX_CLK 71 + #define GCC_PCIE_WIGIG_CLKREF_EN 74 + + phy@1c0e000 { + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; + reg = <0x01c0e000 0x1c0>; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + };
Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml) to qcom,sc8280xp-qmp-pcie-phy.yaml. This removes a need to declare the child PHY node or split resource regions. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 299 ------------------ .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 213 +++++++++++-- 2 files changed, 187 insertions(+), 325 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml