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Tue, 4 Apr 2023 16:50:12 GMT Received: from devipriy-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 4 Apr 2023 09:50:03 -0700 From: Devi Priya To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 9/9] PCI: qcom: Add support for IPQ9574 Date: Tue, 4 Apr 2023 22:18:28 +0530 Message-ID: <20230404164828.8031-10-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230404164828.8031-1-quic_devipriy@quicinc.com> References: <20230404164828.8031-1-quic_devipriy@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: D_sHUbA0nX3JJkbrHU6AWPoigXkrrOIc X-Proofpoint-ORIG-GUID: D_sHUbA0nX3JJkbrHU6AWPoigXkrrOIc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-04_08,2023-04-04_04,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 spamscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304040156 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230404_095019_872639_B9633C23 X-CRM114-Status: GOOD ( 25.33 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The IPQ9574 platform has 4 Gen3 PCIe controllers: two single-lane and two dual-lane based on SNPS core 5.70a The Qcom IP rev is 1.27.0 and Synopsys IP rev is 5.80a Added a new compatible 'qcom,pcie-ipq9574' and 'ops_1_27_0' which reuses all the members of 'ops_2_9_0' except for the post_init as the SLV_ADDR_SPACE_SIZE configuration differs between 2_9_0 and 1_27_0. Also, modified get_resources of 'ops 2_9_0' to get the clocks from the device tree and modelled the post init sequence as a common function to avoid code redundancy Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Signed-off-by: Devi Priya --- Changes in V2: - Updated the commit message with details on the PCIe controller - Updated ops_2_9_0 to get the clocks from the DT - Added ops 1_27_0 for ipq9574 which reuses the functions of existing ops_2_9_0 except for the post init sequence which is modelled as a common function to handle the difference in SLV_ADDR_SPACE_SIZE configuration drivers/pci/controller/dwc/pcie-qcom.c | 62 ++++++++++++++++++-------- 1 file changed, 44 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a232b04af048..b03d182eb283 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -114,6 +114,7 @@ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 +#define SLV_ADDR_SPACE_SZ_1_27_0 0x08000000 #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 @@ -189,8 +190,9 @@ struct qcom_pcie_resources_2_7_0 { }; struct qcom_pcie_resources_2_9_0 { - struct clk_bulk_data clks[5]; + struct clk_bulk_data *clks; struct reset_control *rst; + int num_clks; }; union qcom_pcie_resources { @@ -1308,17 +1310,10 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; - int ret; - res->clks[0].id = "iface"; - res->clks[1].id = "axi_m"; - res->clks[2].id = "axi_s"; - res->clks[3].id = "axi_bridge"; - res->clks[4].id = "rchng"; - - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); - if (ret < 0) - return ret; + res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); + if (res->clks < 0) + return res->num_clks; res->rst = devm_reset_control_array_get_exclusive(dev); if (IS_ERR(res->rst)) @@ -1331,7 +1326,7 @@ static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); } static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) @@ -1360,19 +1355,16 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) usleep_range(2000, 2500); - return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + return clk_bulk_prepare_enable(res->num_clks, res->clks); } -static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) +static int qcom_pcie_post_init(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; int i; - writel(SLV_ADDR_SPACE_SZ, - pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val &= ~BIT(0); writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); @@ -1401,7 +1393,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + - PCI_EXP_DEVCTL2); + PCI_EXP_DEVCTL2); for (i = 0; i < 256; i++) writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i)); @@ -1409,6 +1401,26 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) return 0; } +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie) +{ + writel(SLV_ADDR_SPACE_SZ_1_27_0, + pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); + + qcom_pcie_post_init(pcie); + + return 0; +} + +static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) +{ + writel(SLV_ADDR_SPACE_SZ, + pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); + + qcom_pcie_post_init(pcie); + + return 0; +} + static int qcom_pcie_link_up(struct dw_pcie *pci) { u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); @@ -1620,6 +1632,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */ +static const struct qcom_pcie_ops ops_1_27_0 = { + .get_resources = qcom_pcie_get_resources_2_9_0, + .init = qcom_pcie_init_2_9_0, + .post_init = qcom_pcie_post_init_1_27_0, + .deinit = qcom_pcie_deinit_2_9_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, +}; + static const struct qcom_pcie_cfg cfg_1_0_0 = { .ops = &ops_1_0_0, }; @@ -1652,6 +1673,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = { .ops = &ops_2_9_0, }; +static const struct qcom_pcie_cfg cfg_1_27_0 = { + .ops = &ops_1_27_0, +}; + static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, @@ -1829,6 +1854,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 }, { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },