@@ -8,6 +8,7 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "ipq9574.dtsi"
/ {
@@ -43,6 +44,42 @@
};
};
+&pcie1_phy {
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_1_pin>;
+
+ perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie2_phy {
+ status = "okay";
+};
+
+&pcie2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_2_pin>;
+
+ perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie3_phy {
+ status = "okay";
+};
+
+&pcie3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_3_pin>;
+
+ perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&sdhc_1 {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
@@ -60,6 +97,31 @@
};
&tlmm {
+
+ pcie_1_pin: pcie-1-state {
+ pins = "gpio26";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ output-low;
+ };
+
+ pcie_2_pin: pcie-2-state {
+ pins = "gpio29";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ output-low;
+ };
+
+ pcie_3_pin: pcie-3-state {
+ pins = "gpio32";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-low;
+ };
+
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
Enable the PCIe controller and PHY nodes corresponding to RDP 433 Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> --- Changes in V2: - Moved the Board DT changes to a new patch as suggested - Added pinctrl definitions for PCIe perst GPIOs - Dropped the suffix denoting the lane config from pcie labels arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 62 +++++++++++++++++++++ 1 file changed, 62 insertions(+)