From patchwork Wed Apr 12 08:45:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Changhuang Liang X-Patchwork-Id: 13208646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D4D5C7619A for ; Wed, 12 Apr 2023 08:46:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JJ4OlM5Mt06Jo2BfQW0BfUYA+Ca9VZZ0saGoOcCogg0=; b=XndLIxqTWkLLsj gIbGHzVTPCuAP0S+QOjwq7r/A4sJEec0Sz7XkAcyb3IorJ/sS6hvAAOtdd0nfw1+cl22GEW4tF8Fj A9YMwPNST2a3RaM68cmB50e1oDJhTkSAbkfaY/SfyZ59db9TfbTze3McubtyFQaJMTTHtDN6BzWLu oG6A4URMvqoAfjONe9WZOWZLUxvKw8vUK9gkmuQYp1u3Nvd6dnEWc8A2u6jpSG8DhLjTRAgb0MRnv dxs7jwArJHxBvduBYxs4Ao+T5TilfOiV5VkiZf3T6+udVASHe70V30W7MX5f7HPOT+bS3FS12qeUv mfhj5t/EdJWFq+wioXcA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pmW7N-002Ink-2I; Wed, 12 Apr 2023 08:46:17 +0000 Received: from ex01.ufhost.com ([61.152.239.75]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pmW7E-002Ii4-11; Wed, 12 Apr 2023 08:46:15 +0000 Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 09DA424E1A4; Wed, 12 Apr 2023 16:45:43 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 12 Apr 2023 16:45:42 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 12 Apr 2023 16:45:41 +0800 From: Changhuang Liang To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel CC: Jack Zhu , Changhuang Liang , , , , Subject: [PATCH v4 1/3] dt-bindings: phy: Add starfive,jh7110-dphy-rx Date: Wed, 12 Apr 2023 01:45:38 -0700 Message-ID: <20230412084540.295411-2-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230412084540.295411-1-changhuang.liang@starfivetech.com> References: <20230412084540.295411-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230412_014608_650209_DC876184 X-CRM114-Status: GOOD ( 13.02 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on a M31 IP. Add a binding for it. Signed-off-by: Changhuang Liang --- .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml new file mode 100644 index 000000000000..5fb2f14af816 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive SoC MIPI D-PHY Rx Controller + +maintainers: + - Jack Zhu + - Changhuang Liang + +description: + The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer + CSI camera data. + +properties: + compatible: + const: starfive,jh7110-dphy-rx + + reg: + maxItems: 1 + + clocks: + items: + - description: config clock + - description: reference clock + - description: escape mode transmit clock + + clock-names: + items: + - const: cfg + - const: ref + - const: tx + + resets: + items: + - description: DPHY_HW reset + - description: DPHY_B09_ALWAYS_ON reset + + power-domains: + maxItems: 1 + + lane_maps: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + D-PHY rx controller physical lanes and logic lanes mapping table. + items: + - description: logic lane index point to physical lane clock lane 0 + - description: logic lane index point to physical lane data lane 0 + - description: logic lane index point to physical lane data lane 1 + - description: logic lane index point to physical lane data lane 2 + - description: logic lane index point to physical lane data lane 3 + - description: logic lane index point to physical lane clock lane 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - power-domains + - lane_maps + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@19820000 { + compatible = "starfive,jh7110-dphy-rx"; + reg = <0x19820000 0x10000>; + clocks = <&ispcrg 3>, + <&ispcrg 4>, + <&ispcrg 5>; + clock-names = "cfg", "ref", "tx"; + resets = <&ispcrg 2>, + <&ispcrg 3>; + power-domains = <&dphy_pwrc 1>; + lane_maps = /bits/ 8 <4 0 1 2 3 5>; + #phy-cells = <0>; + };