| Message ID | 20230412112739.160376-21-angelogioacchino.delregno@collabora.com |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | MediaTek Helio X10 - Mailbox, Display, MMC/SD/SDIO | expand |
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: > The PWM at 0x11006000 is the tertiary PWM; unlike PWM0, PWM1, this is > not display specific and can be used as a generic PWM controller. > > This node is left disabled as usage is board-specific. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Applied, thanks! > --- > arch/arm64/boot/dts/mediatek/mt6795.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi > index cf45cb4ad3d2..50d9276d18c6 100644 > --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi > @@ -583,6 +583,25 @@ uart3: serial@11005000 { > status = "disabled"; > }; > > + pwm2: pwm@11006000 { > + compatible = "mediatek,mt6795-pwm"; > + reg = <0 0x11006000 0 0x1000>; > + #pwm-cells = <2>; > + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&topckgen CLK_TOP_PWM_SEL>, > + <&pericfg CLK_PERI_PWM>, > + <&pericfg CLK_PERI_PWM1>, > + <&pericfg CLK_PERI_PWM2>, > + <&pericfg CLK_PERI_PWM3>, > + <&pericfg CLK_PERI_PWM4>, > + <&pericfg CLK_PERI_PWM5>, > + <&pericfg CLK_PERI_PWM6>, > + <&pericfg CLK_PERI_PWM7>; > + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", > + "pwm4", "pwm5", "pwm6", "pwm7"; > + status = "disabled"; > + }; > + > i2c0: i2c@11007000 { > compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; > reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>;
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index cf45cb4ad3d2..50d9276d18c6 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -583,6 +583,25 @@ uart3: serial@11005000 { status = "disabled"; }; + pwm2: pwm@11006000 { + compatible = "mediatek,mt6795-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM>, + <&pericfg CLK_PERI_PWM1>, + <&pericfg CLK_PERI_PWM2>, + <&pericfg CLK_PERI_PWM3>, + <&pericfg CLK_PERI_PWM4>, + <&pericfg CLK_PERI_PWM5>, + <&pericfg CLK_PERI_PWM6>, + <&pericfg CLK_PERI_PWM7>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4", "pwm5", "pwm6", "pwm7"; + status = "disabled"; + }; + i2c0: i2c@11007000 { compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>;
The PWM at 0x11006000 is the tertiary PWM; unlike PWM0, PWM1, this is not display specific and can be used as a generic PWM controller. This node is left disabled as usage is board-specific. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)