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Fri, 19 May 2023 08:57:48 GMT Received: from devipriy-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 19 May 2023 01:57:42 -0700 From: Devi Priya To: , , , , , , , , , , , CC: , , , , , Subject: [PATCH V2 1/2] dt-bindings: phy: qcom,qmp-pcie: Add ipq9574 bindings Date: Fri, 19 May 2023 14:27:22 +0530 Message-ID: <20230519085723.15601-2-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230519085723.15601-1-quic_devipriy@quicinc.com> References: <20230519085723.15601-1-quic_devipriy@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TdZI1NzKyzYUHx3409UMtDBsKFxWmVuY X-Proofpoint-GUID: TdZI1NzKyzYUHx3409UMtDBsKFxWmVuY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-19_05,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 bulkscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 mlxscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305190075 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230519_015752_681943_EC79F84C X-CRM114-Status: GOOD ( 18.13 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add bindings for the PCIe QMP PHYs found on IPQ9574. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Devi Priya --- Changes in V2: - Picked up the R-b tag - Did not convert the clock IDs to numerical values as the clock header (dependent patch) is merged in latest rc1. .../phy/qcom,ipq9574-qmp-pcie-phy.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml new file mode 100644 index 000000000000..7c8012647051 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq9574-qmp-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (PCIe, IPQ9574) + +maintainers: + - Vinod Koul + +description: + The QMP PHY controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + enum: + - qcom,ipq9574-qmp-gen3x1-pcie-phy + - qcom,ipq9574-qmp-gen3x2-pcie-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 5 + + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: anoc_lane + - const: snoc_lane + - const: pipe + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: common + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - "#clock-cells" + - clock-output-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + pcie0_phy: phy@84000 { + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; + reg = <0x00084000 0x1000>; + + clocks = <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane", "pipe"; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <0>; + clock-output-names = "gcc_pcie0_pipe_clk_src"; + + #phy-cells = <0>; + };