diff mbox series

[v2,03/11] arm64: dts: qcom: msm8996: switch UFS QMP PHY to new style of bindings

Message ID 20230521203834.22566-4-dmitry.baryshkov@linaro.org
State Superseded
Headers show
Series phy: qcom-qmp-ufs: convert to newer style of bindings | expand

Commit Message

Dmitry Baryshkov May 21, 2023, 8:38 p.m. UTC
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 25 +++++++++----------------
 1 file changed, 9 insertions(+), 16 deletions(-)

Comments

Konrad Dybcio May 22, 2023, 4:59 p.m. UTC | #1
On 21.05.2023 22:38, Dmitry Baryshkov wrote:
> Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
> resource region, no per-PHY subnodes).
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm64/boot/dts/qcom/msm8996.dtsi | 25 +++++++++----------------
>  1 file changed, 9 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index 2b35cb3f5292..2b65c608a57e 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -726,9 +726,9 @@ gcc: clock-controller@300000 {
>  				 <&pciephy_1>,
>  				 <&pciephy_2>,
>  				 <&ssusb_phy_0>,
> -				 <&ufsphy_lane 0>,
> -				 <&ufsphy_lane 1>,
> -				 <&ufsphy_lane 2>;
> +				 <&ufsphy 0>,
> +				 <&ufsphy 1>,
> +				 <&ufsphy 2>;
>  			clock-names = "cxo",
>  				      "cxo2",
>  				      "sleep_clk",
> @@ -1993,7 +1993,7 @@ ufshc: ufshc@624000 {
>  			reg = <0x00624000 0x2500>;
>  			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
>  
> -			phys = <&ufsphy_lane>;
> +			phys = <&ufsphy>;
>  			phy-names = "ufsphy";
>  
>  			power-domains = <&gcc UFS_GDSC>;
> @@ -2046,25 +2046,18 @@ ufshc: ufshc@624000 {
>  
>  		ufsphy: phy@627000 {
>  			compatible = "qcom,msm8996-qmp-ufs-phy";
> -			reg = <0x00627000 0x1c4>;
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			ranges;
> +			reg = <0x00627000 0x1000>;
>  
>  			clocks = <&gcc GCC_UFS_CLKREF_CLK>;
>  			clock-names = "ref";
>  
>  			resets = <&ufshc 0>;
>  			reset-names = "ufsphy";
> -			status = "disabled";
>  
> -			ufsphy_lane: phy@627400 {
> -				reg = <0x627400 0x12c>,
> -				      <0x627600 0x200>,
> -				      <0x627c00 0x1b4>;
> -				#clock-cells = <1>;
> -				#phy-cells = <0>;
> -			};
> +			#clock-cells = <1>;
> +			#phy-cells = <0>;
> +
> +			status = "disabled";
>  		};
>  
>  		camss: camss@a00000 {
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 2b35cb3f5292..2b65c608a57e 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -726,9 +726,9 @@  gcc: clock-controller@300000 {
 				 <&pciephy_1>,
 				 <&pciephy_2>,
 				 <&ssusb_phy_0>,
-				 <&ufsphy_lane 0>,
-				 <&ufsphy_lane 1>,
-				 <&ufsphy_lane 2>;
+				 <&ufsphy 0>,
+				 <&ufsphy 1>,
+				 <&ufsphy 2>;
 			clock-names = "cxo",
 				      "cxo2",
 				      "sleep_clk",
@@ -1993,7 +1993,7 @@  ufshc: ufshc@624000 {
 			reg = <0x00624000 0x2500>;
 			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 
-			phys = <&ufsphy_lane>;
+			phys = <&ufsphy>;
 			phy-names = "ufsphy";
 
 			power-domains = <&gcc UFS_GDSC>;
@@ -2046,25 +2046,18 @@  ufshc: ufshc@624000 {
 
 		ufsphy: phy@627000 {
 			compatible = "qcom,msm8996-qmp-ufs-phy";
-			reg = <0x00627000 0x1c4>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
+			reg = <0x00627000 0x1000>;
 
 			clocks = <&gcc GCC_UFS_CLKREF_CLK>;
 			clock-names = "ref";
 
 			resets = <&ufshc 0>;
 			reset-names = "ufsphy";
-			status = "disabled";
 
-			ufsphy_lane: phy@627400 {
-				reg = <0x627400 0x12c>,
-				      <0x627600 0x200>,
-				      <0x627c00 0x1b4>;
-				#clock-cells = <1>;
-				#phy-cells = <0>;
-			};
+			#clock-cells = <1>;
+			#phy-cells = <0>;
+
+			status = "disabled";
 		};
 
 		camss: camss@a00000 {