| Message ID | 20230731105759.3997549-8-dmitry.baryshkov@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | phy: qcom-qmp-pcie: convert to newer style of bindings | expand |
On 31.07.2023 12:57, Dmitry Baryshkov wrote: > Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single > resource region, no per-PHY subnodes). > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 36 ++++++++++------------------ > 1 file changed, 12 insertions(+), 24 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 4353f7265877..670092731c6c 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -869,7 +869,7 @@ gcc: clock-controller@100000 { > reg = <0 0x00100000 0 0x1f0000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, > - <0>, <&pcie1_lane>, > + <0>, <&pcie1_phy>, > <0>, <0>, <0>, > <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; > clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", > @@ -2121,7 +2121,7 @@ pcie1: pci@1c08000 { > > clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, > <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, > - <&pcie1_lane>, > + <&pcie1_phy>, > <&rpmhcc RPMH_CXO_CLK>, > <&gcc GCC_PCIE_1_AUX_CLK>, > <&gcc GCC_PCIE_1_CFG_AHB_CLK>, > @@ -2155,7 +2155,7 @@ pcie1: pci@1c08000 { > > power-domains = <&gcc GCC_PCIE_1_GDSC>; > > - phys = <&pcie1_lane>; > + phys = <&pcie1_phy>; > phy-names = "pciephy"; > > pinctrl-names = "default"; > @@ -2171,15 +2171,18 @@ pcie1: pci@1c08000 { > > pcie1_phy: phy@1c0e000 { > compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; > - reg = <0 0x01c0e000 0 0x1c0>; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > + reg = <0 0x01c0e000 0 0x1000>; > clocks = <&gcc GCC_PCIE_1_AUX_CLK>, > <&gcc GCC_PCIE_1_CFG_AHB_CLK>, > <&gcc GCC_PCIE_CLKREF_EN>, > - <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; > - clock-names = "aux", "cfg_ahb", "ref", "refgen"; > + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, > + <&gcc GCC_PCIE_1_PIPE_CLK>; > + clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe"; 1 per line, pretty please? Konrad
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 4353f7265877..670092731c6c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -869,7 +869,7 @@ gcc: clock-controller@100000 { reg = <0 0x00100000 0 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <&pcie1_lane>, + <0>, <&pcie1_phy>, <0>, <0>, <0>, <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", @@ -2121,7 +2121,7 @@ pcie1: pci@1c08000 { clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_lane>, + <&pcie1_phy>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2155,7 +2155,7 @@ pcie1: pci@1c08000 { power-domains = <&gcc GCC_PCIE_1_GDSC>; - phys = <&pcie1_lane>; + phys = <&pcie1_phy>; phy-names = "pciephy"; pinctrl-names = "default"; @@ -2171,15 +2171,18 @@ pcie1: pci@1c08000 { pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; - reg = <0 0x01c0e000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c0e000 0 0x1000>; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe"; + + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; @@ -2188,21 +2191,6 @@ pcie1_phy: phy@1c0e000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie1_lane: phy@1c0e200 { - reg = <0 0x01c0e200 0 0x170>, - <0 0x01c0e400 0 0x200>, - <0 0x01c0ea00 0 0x1f0>, - <0 0x01c0e600 0 0x170>, - <0 0x01c0e800 0 0x200>, - <0 0x01c0ee00 0 0xf4>; - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - #clock-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; }; ipa: ipa@1e40000 {
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 36 ++++++++++------------------ 1 file changed, 12 insertions(+), 24 deletions(-)