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Tue, 29 Aug 2023 10:17:41 -0700 (PDT) Received: from U4.lan ([2001:9e8:b958:3410:8e0c:ed68:cd6c:7cb8]) by smtp.gmail.com with ESMTPSA id a21-20020a1709062b1500b00993cc1242d4sm6115834ejg.151.2023.08.29.10.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 10:17:40 -0700 (PDT) From: Alex Bee To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Lee Jones , Liam Girdwood , Mark Brown , Michael Turquette , Stephen Boyd , Vinod Koul , Kishon Vijay Abraham I Cc: Elaine Zhang , Johan Jonker , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, alsa-devel@alsa-project.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, Alex Bee Subject: [PATCH 17/31] ARM: dts: rockchip: Add CPU resets for RK312x Date: Tue, 29 Aug 2023 19:16:33 +0200 Message-ID: <20230829171647.187787-18-knaerzche@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829171647.187787-1-knaerzche@gmail.com> References: <20230829171647.187787-1-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230829_101743_514383_97BC8EBB X-CRM114-Status: GOOD ( 11.22 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add the reset controls for all 4 cpu cores. Signed-off-by: Alex Bee --- arch/arm/boot/dts/rockchip/rk312x.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk312x.dtsi b/arch/arm/boot/dts/rockchip/rk312x.dtsi index 7aba97b2c990..b195ac525c37 100644 --- a/arch/arm/boot/dts/rockchip/rk312x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk312x.dtsi @@ -34,6 +34,7 @@ cpu0: cpu@f00 { reg = <0xf00>; clock-latency = <40000>; clocks = <&cru ARMCLK>; + resets = <&cru SRST_CORE0>; operating-points = < /* KHz uV */ 816000 1000000 @@ -45,18 +46,21 @@ cpu1: cpu@f01 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf01>; + resets = <&cru SRST_CORE1>; }; cpu2: cpu@f02 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf02>; + resets = <&cru SRST_CORE2>; }; cpu3: cpu@f03 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf03>; + resets = <&cru SRST_CORE3>; }; };