@@ -36,10 +36,7 @@ cpu0: cpu@f00 {
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
resets = <&cru SRST_CORE0>;
- operating-points = <
- /* KHz uV */
- 816000 1000000
- >;
+ operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
};
@@ -48,6 +45,7 @@ cpu1: cpu@f01 {
compatible = "arm,cortex-a7";
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
+ operating-points-v2 = <&cpu_opp_table>;
};
cpu2: cpu@f02 {
@@ -55,6 +53,7 @@ cpu2: cpu@f02 {
compatible = "arm,cortex-a7";
reg = <0xf02>;
resets = <&cru SRST_CORE2>;
+ operating-points-v2 = <&cpu_opp_table>;
};
cpu3: cpu@f03 {
@@ -62,6 +61,42 @@ cpu3: cpu@f03 {
compatible = "arm,cortex-a7";
reg = <0xf03>;
resets = <&cru SRST_CORE3>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ };
+
+ cpu_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-216000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <950000 950000 1325000>;
+ };
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000 950000 1325000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <950000 950000 1325000>;
+ };
+ opp-696000000 {
+ opp-hz = /bits/ 64 <696000000>;
+ opp-microvolt = <975000 975000 1325000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1075000 1075000 1325000>;
+ opp-suspend;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1200000 1200000 1325000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1325000 1325000 1325000>;
};
};
This will allow frequency-scaling for the cpu cores. Operating frequencies and voltages have been taken from Rockchip's downstream kernel. Signed-off-by: Alex Bee <knaerzche@gmail.com> --- arch/arm/boot/dts/rockchip/rk312x.dtsi | 43 +++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 4 deletions(-)