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Tue, 29 Aug 2023 10:17:43 -0700 (PDT) Received: from U4.lan ([2001:9e8:b958:3410:8e0c:ed68:cd6c:7cb8]) by smtp.gmail.com with ESMTPSA id a21-20020a1709062b1500b00993cc1242d4sm6115834ejg.151.2023.08.29.10.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 10:17:42 -0700 (PDT) From: Alex Bee To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Lee Jones , Liam Girdwood , Mark Brown , Michael Turquette , Stephen Boyd , Vinod Koul , Kishon Vijay Abraham I Cc: Elaine Zhang , Johan Jonker , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, alsa-devel@alsa-project.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, Alex Bee Subject: [PATCH 19/31] ARM: dts: rockchip: Switch to operating-points-v2 for RK312x's CPU Date: Tue, 29 Aug 2023 19:16:35 +0200 Message-ID: <20230829171647.187787-20-knaerzche@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829171647.187787-1-knaerzche@gmail.com> References: <20230829171647.187787-1-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230829_101745_514912_642C4669 X-CRM114-Status: GOOD ( 12.44 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This will allow frequency-scaling for the cpu cores. Operating frequencies and voltages have been taken from Rockchip's downstream kernel. Signed-off-by: Alex Bee --- arch/arm/boot/dts/rockchip/rk312x.dtsi | 43 +++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rk312x.dtsi b/arch/arm/boot/dts/rockchip/rk312x.dtsi index 08b953b005ff..93560c4cd16a 100644 --- a/arch/arm/boot/dts/rockchip/rk312x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk312x.dtsi @@ -36,10 +36,7 @@ cpu0: cpu@f00 { clock-latency = <40000>; clocks = <&cru ARMCLK>; resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; + operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ }; @@ -48,6 +45,7 @@ cpu1: cpu@f01 { compatible = "arm,cortex-a7"; reg = <0xf01>; resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu_opp_table>; }; cpu2: cpu@f02 { @@ -55,6 +53,7 @@ cpu2: cpu@f02 { compatible = "arm,cortex-a7"; reg = <0xf02>; resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu_opp_table>; }; cpu3: cpu@f03 { @@ -62,6 +61,42 @@ cpu3: cpu@f03 { compatible = "arm,cortex-a7"; reg = <0xf03>; resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <950000 950000 1325000>; + }; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1325000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1325000>; + }; + opp-696000000 { + opp-hz = /bits/ 64 <696000000>; + opp-microvolt = <975000 975000 1325000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1075000 1075000 1325000>; + opp-suspend; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000 1200000 1325000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1325000 1325000 1325000>; }; };