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[RFC,v2,net-next,05/15] net: add 25GBase-KR-S and 25GBase-CR-S to ethtool link mode UAPI

Message ID 20230923134904.3627402-6-vladimir.oltean@nxp.com
State RFC
Headers show
Series Add C72/C73 copper backplane support for LX2160 | expand

Commit Message

Vladimir Oltean Sept. 23, 2023, 1:48 p.m. UTC 
Some relevant quotes from IEEE 802.3-2018:

Clause 73.6.4 Technology Ability Field:

| 25GBASE-KR-S abilities are a subset of 25GBASE-KR abilities, and
| likewise 25GBASE-CR-S abilities are a subset of 25GBASE-CR abilities.
| To allow interoperation between 25GBASE-KR-S and 25GBASE-KR PHY types,
| and between 25GBASE-CR-S and 25GBASE-CR PHY types, a device that
| supports 25GBASE-KR or 25GBASE-CR should advertise both A9 and A10
| ability bits during auto-negotiation.

Definition 1.4.93 25GBASE-CR-S:

| IEEE 802.3 Physical Layer specification equivalent to 25GBASE-CR without
| support for the RS-FEC sublayer specified in Clause 108.

Definition 1.4.96 25GBASE-KR-S:

| IEEE 802.3 Physical Layer specification equivalent to 25GBASE-KR
| without support for the RS-FEC sublayer specified in Clause 108.

Because Linux already has link modes for the full 25GBase-CR and
25GBase-KR, it makes a lot more sense to increase interoperability in
the way that IEEE recommends, by being able to advertise the subsets
too.

Some of the existing drivers which could make use of this, based on
a keyword search, are:

NFP_MEDIA_25GBASE_KR_S, NFP_MEDIA_25GBASE_CR_S
HINIC_25GE_BASE_KR_S, HINIC_25GE_BASE_CR_S
ICE_PHY_TYPE_LOW_25GBASE_KR_S, ICE_PHY_TYPE_LOW_25GBASE_CR_S

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/phy/phy-core.c   | 2 +-
 include/uapi/linux/ethtool.h | 2 ++
 net/ethtool/common.c         | 6 ++++++
 3 files changed, 9 insertions(+), 1 deletion(-)

Comments

Russell King (Oracle) Oct. 3, 2023, 11:19 a.m. UTC | #1 
On Sat, Sep 23, 2023 at 04:48:54PM +0300, Vladimir Oltean wrote:
> diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
> index f7fba0dc87e5..421eb57fb6e9 100644
> --- a/include/uapi/linux/ethtool.h
> +++ b/include/uapi/linux/ethtool.h
> @@ -1787,6 +1787,8 @@ enum ethtool_link_mode_bit_indices {
>  	ETHTOOL_LINK_MODE_10baseT1S_Full_BIT		 = 99,
>  	ETHTOOL_LINK_MODE_10baseT1S_Half_BIT		 = 100,
>  	ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT	 = 101,
> +	ETHTOOL_LINK_MODE_25000baseCR_S_Full_BIT	 = 102,
> +	ETHTOOL_LINK_MODE_25000baseKR_S_Full_BIT	 = 103,

Should these also be add to phylink_caps_to_linkmodes()'s MAC_25000FD
conditional block?
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Patch

diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 966c93cbe616..5f4e2a120abb 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -13,7 +13,7 @@ 
  */
 const char *phy_speed_to_str(int speed)
 {
-	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 102,
+	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 104,
 		"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
 		"If a speed or mode has been added please update phy_speed_to_str "
 		"and the PHY settings array.\n");
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index f7fba0dc87e5..421eb57fb6e9 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1787,6 +1787,8 @@  enum ethtool_link_mode_bit_indices {
 	ETHTOOL_LINK_MODE_10baseT1S_Full_BIT		 = 99,
 	ETHTOOL_LINK_MODE_10baseT1S_Half_BIT		 = 100,
 	ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT	 = 101,
+	ETHTOOL_LINK_MODE_25000baseCR_S_Full_BIT	 = 102,
+	ETHTOOL_LINK_MODE_25000baseKR_S_Full_BIT	 = 103,
 
 	/* must be last entry */
 	__ETHTOOL_LINK_MODE_MASK_NBITS
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index f5598c5f50de..2b3ddea465af 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -211,10 +211,13 @@  const char link_mode_names[][ETH_GSTRING_LEN] = {
 	__DEFINE_LINK_MODE_NAME(10, T1S, Full),
 	__DEFINE_LINK_MODE_NAME(10, T1S, Half),
 	__DEFINE_LINK_MODE_NAME(10, T1S_P2MP, Half),
+	__DEFINE_LINK_MODE_NAME(25000, CR_S, Full),
+	__DEFINE_LINK_MODE_NAME(25000, KR_S, Full),
 };
 static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
 
 #define __LINK_MODE_LANES_CR		1
+#define __LINK_MODE_LANES_CR_S		1
 #define __LINK_MODE_LANES_CR2		2
 #define __LINK_MODE_LANES_CR4		4
 #define __LINK_MODE_LANES_CR8		8
@@ -223,6 +226,7 @@  static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
 #define __LINK_MODE_LANES_DR4		4
 #define __LINK_MODE_LANES_DR8		8
 #define __LINK_MODE_LANES_KR		1
+#define __LINK_MODE_LANES_KR_S		1
 #define __LINK_MODE_LANES_KR2		2
 #define __LINK_MODE_LANES_KR4		4
 #define __LINK_MODE_LANES_KR8		8
@@ -374,6 +378,8 @@  const struct link_mode_info link_mode_params[] = {
 	__DEFINE_LINK_MODE_PARAMS(10, T1S, Full),
 	__DEFINE_LINK_MODE_PARAMS(10, T1S, Half),
 	__DEFINE_LINK_MODE_PARAMS(10, T1S_P2MP, Half),
+	__DEFINE_LINK_MODE_PARAMS(25000, CR_S, Full),
+	__DEFINE_LINK_MODE_PARAMS(25000, KR_S, Full),
 };
 static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS);