| Message ID | 20240322130646.1016630-2-marcel@ziswiler.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | phy: freescale: imx8m-pcie: facing pcie link-up instability | expand |
> -----Original Message----- > From: Marcel Ziswiler <marcel@ziswiler.com> > Sent: 2024年3月22日 21:07 > To: linux-phy@lists.infradead.org > Cc: dl-linux-imx <linux-imx@nxp.com>; Lucas Stach <l.stach@pengutronix.de>; > linux-arm-kernel@lists.infradead.org; kernel@pengutronix.de; Hongxing Zhu > <hongxing.zhu@nxp.com>; linux-kernel@vger.kernel.org; Marcel Ziswiler > <marcel.ziswiler@toradex.com>; Fabio Estevam <festevam@gmail.com>; Heiko > Stuebner <heiko@sntech.de>; Kishon Vijay Abraham I <kishon@kernel.org>; > Marc Kleine-Budde <mkl@pengutronix.de>; Rob Herring <robh@kernel.org>; > Sascha Hauer <s.hauer@pengutronix.de>; Shawn Guo <shawnguo@kernel.org>; > tharvey@gateworks.com; Vinod Koul <vkoul@kernel.org>; Yang Li > <yang.lee@linux.alibaba.com>; imx@lists.linux.dev > Subject: [PATCH v1 1/1] phy: freescale: imx8m-pcie: fix pcie link-up instability > > From: Marcel Ziswiler <marcel.ziswiler@toradex.com> > > Leaving AUX_PLL_REFCLK_SEL at its reset default of AUX_IN (PLL clock) proves to > be more stable on the i.MX 8M Mini. > > Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone > phy driver") > Hi Marcel I took look back at the validation codes. i.MX8MM PCIe doesn't configure cmn_reg063 (offset: 0x18C) indeed. It's my bad to treat i.MX8MM same as i.MX8MP refer to my assumption on the literal meaning of these bit definitions. Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Best Regards Richard Zhu > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> > --- > > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > index b700f52b7b67..11fcb1867118 100644 > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > @@ -110,8 +110,10 @@ static int imx8_pcie_phy_power_on(struct phy *phy) > /* Source clock from SoC internal PLL */ > writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, > imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); > - writel(AUX_PLL_REFCLK_SEL_SYS_PLL, > - imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); > + if (imx8_phy->drvdata->variant != IMX8MM) { > + writel(AUX_PLL_REFCLK_SEL_SYS_PLL, > + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); > + } > val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; > writel(val | ANA_AUX_RX_TERM_GND_EN, > imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064); > -- > 2.44.0
On 22-03-24, 14:06, Marcel Ziswiler wrote: > From: Marcel Ziswiler <marcel.ziswiler@toradex.com> > > Leaving AUX_PLL_REFCLK_SEL at its reset default of AUX_IN (PLL clock) > proves to be more stable on the i.MX 8M Mini. > > Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver") > Please dont keep an empty line b/w Fixes and s-o-b line... > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> > --- > > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > index b700f52b7b67..11fcb1867118 100644 > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > @@ -110,8 +110,10 @@ static int imx8_pcie_phy_power_on(struct phy *phy) > /* Source clock from SoC internal PLL */ > writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, > imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); > - writel(AUX_PLL_REFCLK_SEL_SYS_PLL, > - imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); > + if (imx8_phy->drvdata->variant != IMX8MM) { > + writel(AUX_PLL_REFCLK_SEL_SYS_PLL, > + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); > + } > val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; > writel(val | ANA_AUX_RX_TERM_GND_EN, > imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064); > -- > 2.44.0 > > > -- > linux-phy mailing list > linux-phy@lists.infradead.org > https://lists.infradead.org/mailman/listinfo/linux-phy
On 22-03-24, 14:06, Marcel Ziswiler wrote: > From: Marcel Ziswiler <marcel.ziswiler@toradex.com> > > Leaving AUX_PLL_REFCLK_SEL at its reset default of AUX_IN (PLL clock) > proves to be more stable on the i.MX 8M Mini. This doesn't apply on phy/fixes Please rebase
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c index b700f52b7b67..11fcb1867118 100644 --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c @@ -110,8 +110,10 @@ static int imx8_pcie_phy_power_on(struct phy *phy) /* Source clock from SoC internal PLL */ writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); - writel(AUX_PLL_REFCLK_SEL_SYS_PLL, - imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); + if (imx8_phy->drvdata->variant != IMX8MM) { + writel(AUX_PLL_REFCLK_SEL_SYS_PLL, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); + } val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; writel(val | ANA_AUX_RX_TERM_GND_EN, imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);