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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240422_091627_915328_F77E04E3 X-CRM114-Status: UNSURE ( 9.79 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy provided QMP_PCIE_PHY_AUX_CLK. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 19 ------------------- arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++--------- 4 files changed, 4 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 12d60a0ee095..ccff744dcd14 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -979,10 +979,6 @@ &pcie1_phy { status = "okay"; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins = "gpio12"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 3d4ad5aac70f..1fa7c4492057 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -739,10 +739,6 @@ &mdss_dp0_out { remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 92f015017418..39ba3e9969b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -720,17 +720,6 @@ &ipa { status = "okay"; }; -&gcc { - clocks = <&bi_tcxo_div2>, <&sleep_clk>, - <&pcie0_phy>, - <&pcie1_phy>, - <0>, - <&ufs_mem_phy 0>, - <&ufs_mem_phy 1>, - <&ufs_mem_phy 2>, - <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; -}; - &gpi_dma1 { status = "okay"; }; @@ -810,10 +799,6 @@ &mdss_dp0_out { remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; -&pcie_1_phy_aux_clk { - status = "disabled"; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; @@ -907,10 +892,6 @@ &pon_resin { status = "okay"; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index bc5aeb05ffc3..143994d1e6ca 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -58,11 +58,6 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-mult = <1>; clock-div = <2>; }; - - pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; }; cpus { @@ -776,8 +771,8 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; clocks = <&bi_tcxo_div2>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <&pcie_1_phy_aux_clk>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -1928,8 +1923,8 @@ pcie1_phy: phy@1c0e000 { power-domains = <&gcc PCIE_1_PHY_GDSC>; - #clock-cells = <0>; - clock-output-names = "pcie1_pipe_clk"; + #clock-cells = <1>; + clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk"; #phy-cells = <0>;