| Message ID | 20240902111127.15155-2-minda.chen@starfivetech.com |
|---|---|
| State | New |
| Headers | show |
| Series | Fix configuration for on-chip USB 2.0 support | expand |
On Mon, Sep 02, 2024 at 07:11:27PM +0800, Minda Chen wrote: > From: Jan Kiszka <jan.kiszka@siemens.com> > > In order to connect the USB 2.0 PHY to its controller, we also need to > set "u0_pdrstn_split_sw_usbpipe_plugen" [1]. Some downstream U-Boot > versions did that, but upstream firmware does not, and the kernel must > not rely on such behavior anyway. Failing to set this left the USB > gadget port invisible to connected hosts behind. > > Link: https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/sys_syscon.html#sys_syscon__section_b3l_fqs_wsb [1] > Fixes: 16d3a71c20cf ("phy: starfive: Add JH7110 USB 2.0 PHY driver") > Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > On Mon, Sep 02, 2024 at 07:11:27PM +0800, Minda Chen wrote: > > From: Jan Kiszka <jan.kiszka@siemens.com> > > > > In order to connect the USB 2.0 PHY to its controller, we also need to > > set "u0_pdrstn_split_sw_usbpipe_plugen" [1]. Some downstream U-Boot > > versions did that, but upstream firmware does not, and the kernel must > > not rely on such behavior anyway. Failing to set this left the USB > > gadget port invisible to connected hosts behind. > > > > Link: > > https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/sys_syscon.html#sys_s > > yscon__section_b3l_fqs_wsb [1] > > Fixes: 16d3a71c20cf ("phy: starfive: Add JH7110 USB 2.0 PHY driver") > > Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Conor : Thanks
Minda Chen wrote: > From: Jan Kiszka <jan.kiszka@siemens.com> > > In order to connect the USB 2.0 PHY to its controller, we also need to > set "u0_pdrstn_split_sw_usbpipe_plugen" [1]. Some downstream U-Boot > versions did that, but upstream firmware does not, and the kernel must > not rely on such behavior anyway. Failing to set this left the USB > gadget port invisible to connected hosts behind. > > Link: https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/sys_syscon.html#sys_syscon__section_b3l_fqs_wsb [1] > Fixes: 16d3a71c20cf ("phy: starfive: Add JH7110 USB 2.0 PHY driver") > Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Apologies if this was already applied somewhere, but I don't see message that it was. In any case this looks good to me, thanks. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > --- > drivers/phy/starfive/phy-jh7110-usb.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/phy/starfive/phy-jh7110-usb.c b/drivers/phy/starfive/phy-jh7110-usb.c > index 633912f8a05d..dabe59953070 100644 > --- a/drivers/phy/starfive/phy-jh7110-usb.c > +++ b/drivers/phy/starfive/phy-jh7110-usb.c > @@ -10,18 +10,24 @@ > #include <linux/clk.h> > #include <linux/err.h> > #include <linux/io.h> > +#include <linux/mfd/syscon.h> > #include <linux/module.h> > #include <linux/phy/phy.h> > #include <linux/platform_device.h> > +#include <linux/regmap.h> > #include <linux/usb/of.h> > > #define USB_125M_CLK_RATE 125000000 > #define USB_LS_KEEPALIVE_OFF 0x4 > #define USB_LS_KEEPALIVE_ENABLE BIT(4) > > +#define USB_PDRSTN_SPLIT BIT(17) > +#define SYSCON_USB_SPLIT_OFFSET 0x18 > + > struct jh7110_usb2_phy { > struct phy *phy; > void __iomem *regs; > + struct regmap *sys_syscon; > struct clk *usb_125m_clk; > struct clk *app_125m; > enum phy_mode mode; > @@ -61,6 +67,10 @@ static int usb2_phy_set_mode(struct phy *_phy, > usb2_set_ls_keepalive(phy, (mode != PHY_MODE_USB_DEVICE)); > } > > + /* Connect usb 2.0 phy mode */ > + regmap_update_bits(phy->sys_syscon, SYSCON_USB_SPLIT_OFFSET, > + USB_PDRSTN_SPLIT, USB_PDRSTN_SPLIT); > + > return 0; > } > > @@ -129,6 +139,12 @@ static int jh7110_usb_phy_probe(struct platform_device *pdev) > phy_set_drvdata(phy->phy, phy); > phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); > > + phy->sys_syscon = > + syscon_regmap_lookup_by_compatible("starfive,jh7110-sys-syscon"); > + if (IS_ERR(phy->sys_syscon)) > + return dev_err_probe(dev, PTR_ERR(phy->sys_syscon), > + "Failed to get sys-syscon\n"); > + > return PTR_ERR_OR_ZERO(phy_provider); > } > > -- > 2.17.1 >
diff --git a/drivers/phy/starfive/phy-jh7110-usb.c b/drivers/phy/starfive/phy-jh7110-usb.c index 633912f8a05d..dabe59953070 100644 --- a/drivers/phy/starfive/phy-jh7110-usb.c +++ b/drivers/phy/starfive/phy-jh7110-usb.c @@ -10,18 +10,24 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> +#include <linux/regmap.h> #include <linux/usb/of.h> #define USB_125M_CLK_RATE 125000000 #define USB_LS_KEEPALIVE_OFF 0x4 #define USB_LS_KEEPALIVE_ENABLE BIT(4) +#define USB_PDRSTN_SPLIT BIT(17) +#define SYSCON_USB_SPLIT_OFFSET 0x18 + struct jh7110_usb2_phy { struct phy *phy; void __iomem *regs; + struct regmap *sys_syscon; struct clk *usb_125m_clk; struct clk *app_125m; enum phy_mode mode; @@ -61,6 +67,10 @@ static int usb2_phy_set_mode(struct phy *_phy, usb2_set_ls_keepalive(phy, (mode != PHY_MODE_USB_DEVICE)); } + /* Connect usb 2.0 phy mode */ + regmap_update_bits(phy->sys_syscon, SYSCON_USB_SPLIT_OFFSET, + USB_PDRSTN_SPLIT, USB_PDRSTN_SPLIT); + return 0; } @@ -129,6 +139,12 @@ static int jh7110_usb_phy_probe(struct platform_device *pdev) phy_set_drvdata(phy->phy, phy); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + phy->sys_syscon = + syscon_regmap_lookup_by_compatible("starfive,jh7110-sys-syscon"); + if (IS_ERR(phy->sys_syscon)) + return dev_err_probe(dev, PTR_ERR(phy->sys_syscon), + "Failed to get sys-syscon\n"); + return PTR_ERR_OR_ZERO(phy_provider); }