| Message ID | 20240903013113.139698-5-aford173@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | phy: freescale: fsl-samsung-hdmi: Expand phy clock options | expand |
Thank you! Adam Ford wrote on Mon, Sep 02, 2024 at 08:30:46PM -0500: > + /* Calculate the differences and use the closest one */ > + delta_frac = (rate - phy_pll_cfg[i].pixclk); > + delta_int = (rate - int_div_clk); This assumes rate > whatever pixclk was found, that doesn't look true to me for the integer calculation (`delta = abs(fout - tmp)` so it looks like it can pick a larger value) For the LUT, the way the lookup works is by picking the closest smaller value so this is not a problem, but someone might come fix that later so I'd rather just use abs() everywhere for future-proofing That aside it looks good to me, I'll add a 0.5% tolerance patch and test this all ASAP (might be a few days); will send the tolerance patch properly after testing but for reference it will probably look like this: --- From 12479386c955a59330232c84f4f856606c3a53e0 Mon Sep 17 00:00:00 2001 From: Dominique Martinet <dominique.martinet@atmark-techno.com> Date: Tue, 3 Sep 2024 13:47:24 +0900 Subject: [PATCH] drm/bridge: imx8mp-hdmi-tx: allow 0.5% margin with selected clock This allows the hdmi driver to pick e.g. 64.8MHz instead of 65Mhz when we cannot output the exact frequency, enabling the imx8mp HDMI output to support more modes Signed-off-by: Dominique Martinet <dominique.martinet@atmark-techno.com> diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c index 13bc570c5473..9431cd5e06c3 100644 --- a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c +++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c @@ -23,6 +23,7 @@ imx8mp_hdmi_mode_valid(struct dw_hdmi *dw_hdmi, void *data, const struct drm_display_mode *mode) { struct imx8mp_hdmi *hdmi = (struct imx8mp_hdmi *)data; + long round_rate; if (mode->clock < 13500) return MODE_CLOCK_LOW; @@ -30,8 +31,9 @@ imx8mp_hdmi_mode_valid(struct dw_hdmi *dw_hdmi, void *data, if (mode->clock > 297000) return MODE_CLOCK_HIGH; - if (clk_round_rate(hdmi->pixclk, mode->clock * 1000) != - mode->clock * 1000) + round_rate = clk_round_rate(hdmi->pixclk, mode->clock * 1000); + /* accept 0.5% = 5/1000 tolerance (mode->clock is 1/1000) */ + if (abs(round_rate - mode->clock * 1000) > mode->clock * 5) return MODE_CLOCK_RANGE; /* We don't support double-clocked and Interlaced modes */ --- -- Dominique
diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index 8822029526f0..0bf526e282a7 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -541,7 +541,7 @@ static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, static long phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - u32 int_div_clk; + u32 int_div_clk, delta_int, delta_frac; int i; u16 m; u8 p, s; @@ -554,6 +554,7 @@ static long phy_clk_round_rate(struct clk_hw *hw, for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) if (phy_pll_cfg[i].pixclk <= rate) break; + /* If the rate is an exact match, return it now */ if (rate == phy_pll_cfg[i].pixclk) return phy_pll_cfg[i].pixclk; @@ -570,15 +571,21 @@ static long phy_clk_round_rate(struct clk_hw *hw, if (int_div_clk == rate) return int_div_clk; - /* Fall back to the closest value in the LUT */ - return phy_pll_cfg[i].pixclk; + /* Calculate the differences and use the closest one */ + delta_frac = (rate - phy_pll_cfg[i].pixclk); + delta_int = (rate - int_div_clk); + + if (delta_int < delta_frac) + return int_div_clk; + else + return phy_pll_cfg[i].pixclk; } static int phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw); - u32 int_div_clk; + u32 int_div_clk, delta_int, delta_frac; int i; u16 m; u8 p, s; @@ -593,19 +600,34 @@ static int phy_clk_set_rate(struct clk_hw *hw, calculated_phy_pll_cfg.pll_div_regs[2] = FIELD_PREP(REG03_PMS_S_MASK, s-1); /* pll_div_regs 3-6 are fixed and pre-defined already */ phy->cur_cfg = &calculated_phy_pll_cfg; + goto done; } else { /* Otherwise, search the LUT */ - dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider\n"); - for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) - if (phy_pll_cfg[i].pixclk <= rate) + for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) { + if (phy_pll_cfg[i].pixclk == rate) { + dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider\n"); + phy->cur_cfg = &phy_pll_cfg[i]; + goto done; + } + + if (phy_pll_cfg[i].pixclk < rate) break; + } if (i < 0) return -EINVAL; - - phy->cur_cfg = &phy_pll_cfg[i]; } + /* Calculate the differences for each clock against the requested value */ + delta_frac = (rate - phy_pll_cfg[i].pixclk); + delta_int = (rate - int_div_clk); + + /* Use the value closest to the desired */ + if (delta_int < delta_frac) + phy->cur_cfg = &calculated_phy_pll_cfg; + else + phy->cur_cfg = &phy_pll_cfg[i]; +done: return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); }
Currently, if the clock values cannot be set to the exact rate, the round_rate and set_rate functions use the closest value found in the look-up-table. In preparation of removing values from the LUT that can be calculated evenly with the integer calculator, it's necessary to ensure to check both the look-up-table and the integer divider clock values to get the closest values to the requested value. It does this by measuring the difference between the requested clock value and the closest value in both integer divider calucator and the fractional clock look-up-table. Which ever has the smallest difference between them is returned as the cloesest rate. Signed-off-by: Adam Ford <aford173@gmail.com> --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 40 +++++++++++++++----- 1 file changed, 31 insertions(+), 9 deletions(-)