| Message ID | 20240910070339.4150883-5-xu.yang_2@nxp.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v4,1/5] dt-bindings: phy: imx8mq-usb: add compatible "fsl,imx95-usb-phy" | expand |
On Tue, Sep 10, 2024 at 03:03:39PM +0800, Xu Yang wrote: > This board has one Type-C port which has USB3 capability. This will > add typec nodes and enable usb3 node. > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> > > --- > Changes in v2: > - no changes > Changes in v3: > - no changes > Changes in v4: > - no changes > --- > .../boot/dts/freescale/imx95-19x19-evk.dts | 81 +++++++++++++++++++ > 1 file changed, 81 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts > index d14a54ab4fd4..46a9cd3d4403 100644 > --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts > @@ -5,6 +5,7 @@ > > /dts-v1/; > > +#include <dt-bindings/usb/pd.h> > #include "imx95.dtsi" > > / { > @@ -99,6 +100,48 @@ i2c7_pcal6524: i2c7-gpio@22 { > interrupt-parent = <&gpio5>; > interrupts = <16 IRQ_TYPE_LEVEL_LOW>; > }; > + > + ptn5110: tcpc@50 { > + compatible = "nxp,ptn5110", "tcpci"; > + reg = <0x50>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_typec>; > + interrupt-parent = <&gpio5>; > + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; > + > + typec_con: connector { > + compatible = "usb-c-connector"; > + label = "USB-C"; > + power-role = "dual"; > + data-role = "dual"; > + try-power-role = "sink"; > + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; > + sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; > + op-sink-microwatt = <0>; > + self-powered; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + typec_con_hs: endpoint { > + remote-endpoint = <&usb3_data_hs>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + typec_con_ss: endpoint { > + remote-endpoint = <&usb3_data_ss>; > + }; > + }; > + }; > + }; > + }; > }; > > &lpuart1 { > @@ -128,6 +171,38 @@ &pcie1 { > status = "okay"; > }; > > +&usb3 { > + status = "okay"; > +}; > + > +&usb3_phy { > + status = "okay"; > + > + port { > + usb3_data_ss: endpoint { > + remote-endpoint = <&typec_con_ss>; > + }; > + }; > +}; Please keep node name alphabet order usb3_phy should be after usb3_dwc3. Frank > + > +&usb3_dwc3 { > + dr_mode = "otg"; > + hnp-disable; > + srp-disable; > + adp-disable; > + usb-role-switch; > + role-switch-default-mode = "peripheral"; > + snps,dis-u1-entry-quirk; > + snps,dis-u2-entry-quirk; > + status = "okay"; > + > + port { > + usb3_data_hs: endpoint { > + remote-endpoint = <&typec_con_hs>; > + }; > + }; > +}; > + > &usdhc1 { > pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; > pinctrl-0 = <&pinctrl_usdhc1>; > @@ -245,6 +320,12 @@ IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e > >; > }; > > + pinctrl_typec: typecgrp { > + fsl,pins = < > + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e > + >; > + }; > + > pinctrl_usdhc2_gpio: usdhc2gpiogrp { > fsl,pins = < > IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e > -- > 2.34.1 >
On Tue, Sep 10, 2024 at 03:14:50PM -0400, Frank Li wrote: > On Tue, Sep 10, 2024 at 03:03:39PM +0800, Xu Yang wrote: > > This board has one Type-C port which has USB3 capability. This will > > add typec nodes and enable usb3 node. > > > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> > > > > --- > > Changes in v2: > > - no changes > > Changes in v3: > > - no changes > > Changes in v4: > > - no changes > > --- > > .../boot/dts/freescale/imx95-19x19-evk.dts | 81 +++++++++++++++++++ > > 1 file changed, 81 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts > > index d14a54ab4fd4..46a9cd3d4403 100644 > > --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts > > +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts > > @@ -5,6 +5,7 @@ > > > > /dts-v1/; > > > > +#include <dt-bindings/usb/pd.h> > > #include "imx95.dtsi" > > > > / { > > @@ -99,6 +100,48 @@ i2c7_pcal6524: i2c7-gpio@22 { > > interrupt-parent = <&gpio5>; > > interrupts = <16 IRQ_TYPE_LEVEL_LOW>; > > }; > > + > > + ptn5110: tcpc@50 { > > + compatible = "nxp,ptn5110", "tcpci"; > > + reg = <0x50>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_typec>; > > + interrupt-parent = <&gpio5>; > > + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; > > + > > + typec_con: connector { > > + compatible = "usb-c-connector"; > > + label = "USB-C"; > > + power-role = "dual"; > > + data-role = "dual"; > > + try-power-role = "sink"; > > + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; > > + sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; > > + op-sink-microwatt = <0>; > > + self-powered; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + > > + typec_con_hs: endpoint { > > + remote-endpoint = <&usb3_data_hs>; > > + }; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + > > + typec_con_ss: endpoint { > > + remote-endpoint = <&usb3_data_ss>; > > + }; > > + }; > > + }; > > + }; > > + }; > > }; > > > > &lpuart1 { > > @@ -128,6 +171,38 @@ &pcie1 { > > status = "okay"; > > }; > > > > +&usb3 { > > + status = "okay"; > > +}; > > + > > +&usb3_phy { > > + status = "okay"; > > + > > + port { > > + usb3_data_ss: endpoint { > > + remote-endpoint = <&typec_con_ss>; > > + }; > > + }; > > +}; > > Please keep node name alphabet order > usb3_phy should be after usb3_dwc3. Okay. Will fix the order. Thanks, Xu Yang
diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index d14a54ab4fd4..46a9cd3d4403 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/usb/pd.h> #include "imx95.dtsi" / { @@ -99,6 +100,48 @@ i2c7_pcal6524: i2c7-gpio@22 { interrupt-parent = <&gpio5>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; + op-sink-microwatt = <0>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; }; &lpuart1 { @@ -128,6 +171,38 @@ &pcie1 { status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "peripheral"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -245,6 +320,12 @@ IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e >; }; + pinctrl_typec: typecgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
This board has one Type-C port which has USB3 capability. This will add typec nodes and enable usb3 node. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> --- Changes in v2: - no changes Changes in v3: - no changes Changes in v4: - no changes --- .../boot/dts/freescale/imx95-19x19-evk.dts | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+)