| Message ID | 20240911012838.944630-3-aford173@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | phy: freescale: fsl-samsung-hdmi: Expand phy clock options | expand |
Adam Ford wrote on Tue, Sep 10, 2024 at 08:28:08PM -0500: > The value of 'S' is writen to two places, PHY_REG3[7:4] and > PHY_REG21[3:0]. There is a lookup table which contains > the value of PHY_REG3. Rather than using a switch statement > based on the pixel clock to search for the value of 'S' again, > just shift the contents of PHY_REG3[7:4] >> 4 and place the value > in PHY_REG21[3:0]. Doing this can eliminate an entire function. > > Signed-off-by: Adam Ford <aford173@gmail.com> > Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> > Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> > Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> > --- > drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 39 ++------------------ > 1 file changed, 4 insertions(+), 35 deletions(-) > > diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c > index acea7008aefc..4f6874226f9a 100644 > --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c > +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c > @@ -364,40 +364,6 @@ to_fsl_samsung_hdmi_phy(struct clk_hw *hw) > return container_of(hw, struct fsl_samsung_hdmi_phy, hw); > } > > -static void > -fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy, > - const struct phy_config *cfg) > -{ > - u8 div = 0x1; > - > - switch (cfg->pixclk) { > - case 22250000 ... 33750000: > - div = 0xf; > - break; > - case 35000000 ... 40000000: > - div = 0xb; > - break; > - case 43200000 ... 47500000: > - div = 0x9; > - break; > - case 50349650 ... 63500000: > - div = 0x7; > - break; > - case 67500000 ... 90000000: > - div = 0x5; > - break; > - case 94000000 ... 148500000: > - div = 0x3; > - break; > - case 154000000 ... 297000000: > - div = 0x1; > - break; > - } > - > - writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div), > - phy->regs + PHY_REG(21)); > -} > - > static void > fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, > const struct phy_config *cfg) > @@ -466,7 +432,10 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, > for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++) > writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4); > > - fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg); > + /* High nibble of pll_div_regs[1] contains S which also gets written to REG21 */ > + writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, > + cfg->pll_div_regs[1] >> 4), phy->regs + PHY_REG(21)); > + > fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); > > writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));
diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index acea7008aefc..4f6874226f9a 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -364,40 +364,6 @@ to_fsl_samsung_hdmi_phy(struct clk_hw *hw) return container_of(hw, struct fsl_samsung_hdmi_phy, hw); } -static void -fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy, - const struct phy_config *cfg) -{ - u8 div = 0x1; - - switch (cfg->pixclk) { - case 22250000 ... 33750000: - div = 0xf; - break; - case 35000000 ... 40000000: - div = 0xb; - break; - case 43200000 ... 47500000: - div = 0x9; - break; - case 50349650 ... 63500000: - div = 0x7; - break; - case 67500000 ... 90000000: - div = 0x5; - break; - case 94000000 ... 148500000: - div = 0x3; - break; - case 154000000 ... 297000000: - div = 0x1; - break; - } - - writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div), - phy->regs + PHY_REG(21)); -} - static void fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, const struct phy_config *cfg) @@ -466,7 +432,10 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++) writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4); - fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg); + /* High nibble of pll_div_regs[1] contains S which also gets written to REG21 */ + writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, + cfg->pll_div_regs[1] >> 4), phy->regs + PHY_REG(21)); + fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));