| Message ID | 20240923125713.3411487-3-quic_qianyu@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for PCIe3 on x1e80100 | expand |
On Mon, Sep 23, 2024 at 05:57:09AM GMT, Qiang Yu wrote: > Add OPP table so that PCIe is able to adjust power domain performance > state and ICC peak bw according to PCIe gen speed and link width. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- > Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml > index 704c0f58eea5..3c6430fe9331 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml > @@ -78,6 +78,10 @@ properties: > description: GPIO controlled connection to WAKE# signal > maxItems: 1 > > + operating-points-v2: true > + opp-table: > + type: object > + > required: > - reg > - reg-names Please drop it from qcom,pcie-sm8450.yaml, it's redundant now. > -- > 2.34.1 > > > -- > linux-phy mailing list > linux-phy@lists.infradead.org > https://lists.infradead.org/mailman/listinfo/linux-phy
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 704c0f58eea5..3c6430fe9331 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -78,6 +78,10 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + operating-points-v2: true + opp-table: + type: object + required: - reg - reg-names
Add OPP table so that PCIe is able to adjust power domain performance state and ICC peak bw according to PCIe gen speed and link width. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> --- Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 4 ++++ 1 file changed, 4 insertions(+)