| Message ID | 20241012053937.3596885-1-s-vadapalli@ti.com |
|---|---|
| State | Accepted |
| Commit | b4b32423b6ee6bb96e19fd82bcfd372f6192c737 |
| Headers | show |
| Series | [v3] phy: ti: phy-j721e-wiz: fix usxgmii configuration | expand |
On Sat, 12 Oct 2024 11:09:37 +0530, Siddharth Vadapalli wrote: > Commit b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in > wiz driver") added support for USXGMII mode. In doing so, P0_REFCLK_SEL > was set to "pcs_mac_clk_divx1_ln_0" (0x3) and P0_STANDARD_MODE was set to > LANE_MODE_GEN1, which results in a data rate of 5.15625 Gbps. However, > since the USXGMII mode can support up to 10.3125 Gbps data rate, the > aforementioned fields should be set to "pcs_mac_clk_divx0_ln_0" (0x2) and > LANE_MODE_GEN2 respectively. The signal corresponding to the USXGMII lane > of the SERDES has been measured as 5 Gbps without the change and 10 Gbps > with the change. Hence, fix the configuration accordingly to support > USXGMII up to 10G. > > [...] Applied, thanks! [1/1] phy: ti: phy-j721e-wiz: fix usxgmii configuration commit: b4b32423b6ee6bb96e19fd82bcfd372f6192c737 Best regards,
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index a6c0c5607ffd..c6e846d385d2 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -450,8 +450,8 @@ static int wiz_mode_select(struct wiz *wiz) } else if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3); ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3); - ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3); - mode = LANE_MODE_GEN1; + ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x2); + mode = LANE_MODE_GEN2; } else { continue; }
Commit b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver") added support for USXGMII mode. In doing so, P0_REFCLK_SEL was set to "pcs_mac_clk_divx1_ln_0" (0x3) and P0_STANDARD_MODE was set to LANE_MODE_GEN1, which results in a data rate of 5.15625 Gbps. However, since the USXGMII mode can support up to 10.3125 Gbps data rate, the aforementioned fields should be set to "pcs_mac_clk_divx0_ln_0" (0x2) and LANE_MODE_GEN2 respectively. The signal corresponding to the USXGMII lane of the SERDES has been measured as 5 Gbps without the change and 10 Gbps with the change. Hence, fix the configuration accordingly to support USXGMII up to 10G. Fixes: b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> --- Hello, This patch is based on commit 09f6b0c8904b Merge tag 'linux_kselftest-fixes-6.12-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest of the master branch of Mainline Linux. v2: https://lore.kernel.org/r/20240930095745.3007057-1-s-vadapalli@ti.com/ Changes since v2: - Rebased to commit 09f6b0c8904b of Mainline Linux. - Updated commit message based on Roger's feedback. - Collected Reviewed-by tag from Roger Quadros <rogerq@kernel.org> v1: https://lore.kernel.org/r/20240910091714.1082191-1-s-vadapalli@ti.com/ Changes since v1: - Rebased to Linux 6.12-rc1. drivers/phy/ti/phy-j721e-wiz.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)