| Message ID | 20241018-phy-qcom-qmp-pcie-fix-x1e80100-gen4x4-resets-v1-1-f543267a2dd8@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix X1E80100 resets entries | expand |
On Fri, Oct 18, 2024 at 04:37:36PM +0300, Abel Vesa wrote: > The PCIe 6a PHY on X1E80100 uses both resets in 4-lanes mode as well. Again, this is a bit misleading as PCIe6a is using the 'qcom,x1e80100-qmp-gen4x4-pcie-phy' compatible in both 4-lane and 2-lane mode even if the original dtsi got this wrong. PCIe6b will be using 'qcom,x1e80100-qmp-gen4x2-pcie-phy' as that one is a 2-lane PHY. Perhaps you can rephrase this so that it doesn't sound like you are using compatibles to configure PCIe6a? > So fix the resets entries for it by adding the Gen4 4-lanes compatible > alongside the 2-lanes one. > > Fixes: 0c5f4d23f776 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4") > Reported-by: kernel test robot <lkp@intel.com> > Closes: https://lore.kernel.org/oe-kbuild-all/202410182029.n2zPkuGx-lkp@intel.com/ > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Patch itself looks good. Johan
On Fri, Oct 18, 2024 at 04:37:36PM +0300, Abel Vesa wrote: > The PCIe 6a PHY on X1E80100 uses both resets in 4-lanes mode as well. > So fix the resets entries for it by adding the Gen4 4-lanes compatible > alongside the 2-lanes one. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 24-10-21 09:33:20, Johan Hovold wrote: > On Fri, Oct 18, 2024 at 04:37:36PM +0300, Abel Vesa wrote: > > The PCIe 6a PHY on X1E80100 uses both resets in 4-lanes mode as well. > > Again, this is a bit misleading as PCIe6a is using the > 'qcom,x1e80100-qmp-gen4x4-pcie-phy' compatible in both 4-lane and 2-lane > mode even if the original dtsi got this wrong. But the lane config within the phy driver differs based on the compatible. > > PCIe6b will be using 'qcom,x1e80100-qmp-gen4x2-pcie-phy' as that one is > a 2-lane PHY. Wouldn't the PCIe6a also have to switch to gen4x2 compatible on a board where PCIe6b is used? > > Perhaps you can rephrase this so that it doesn't sound like you are > using compatibles to configure PCIe6a? But currently we do configure PCIe6a based on compatibles. What am I missing ? > > > So fix the resets entries for it by adding the Gen4 4-lanes compatible > > alongside the 2-lanes one. > > > > Fixes: 0c5f4d23f776 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4") > > Reported-by: kernel test robot <lkp@intel.com> > > Closes: https://lore.kernel.org/oe-kbuild-all/202410182029.n2zPkuGx-lkp@intel.com/ > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > Patch itself looks good. > > Johan
On Mon, Oct 21, 2024 at 11:53:31AM +0300, Abel Vesa wrote: > On 24-10-21 09:33:20, Johan Hovold wrote: > > On Fri, Oct 18, 2024 at 04:37:36PM +0300, Abel Vesa wrote: > > > The PCIe 6a PHY on X1E80100 uses both resets in 4-lanes mode as well. > > > > Again, this is a bit misleading as PCIe6a is using the > > 'qcom,x1e80100-qmp-gen4x4-pcie-phy' compatible in both 4-lane and 2-lane > > mode even if the original dtsi got this wrong. > > But the lane config within the phy driver differs based on the > compatible. No, it differs based on the value of the TCSR register. > > PCIe6b will be using 'qcom,x1e80100-qmp-gen4x2-pcie-phy' as that one is > > a 2-lane PHY. > > Wouldn't the PCIe6a also have to switch to gen4x2 compatible on a board > where PCIe6b is used? Nope, it stays the same (e.g. as the hardware block is the same). > > Perhaps you can rephrase this so that it doesn't sound like you are > > using compatibles to configure PCIe6a? > > But currently we do configure PCIe6a based on compatibles. > > What am I missing ? No, as we've discussed in multiple threads already: https://lore.kernel.org/all/ZwPDxd9JJbgDeJTi@hovoldconsulting.com/ https://lore.kernel.org/lkml/ZtG2dUVkdwBpBbix@hovoldconsulting.com/ Johan
On 24-10-21 10:59:54, Johan Hovold wrote: > On Mon, Oct 21, 2024 at 11:53:31AM +0300, Abel Vesa wrote: > > On 24-10-21 09:33:20, Johan Hovold wrote: > > > On Fri, Oct 18, 2024 at 04:37:36PM +0300, Abel Vesa wrote: > > > > The PCIe 6a PHY on X1E80100 uses both resets in 4-lanes mode as well. > > > > > > Again, this is a bit misleading as PCIe6a is using the > > > 'qcom,x1e80100-qmp-gen4x4-pcie-phy' compatible in both 4-lane and 2-lane > > > mode even if the original dtsi got this wrong. > > > > But the lane config within the phy driver differs based on the > > compatible. > > No, it differs based on the value of the TCSR register. Yep, realized that now. Thanks for confirming. > > > > PCIe6b will be using 'qcom,x1e80100-qmp-gen4x2-pcie-phy' as that one is > > > a 2-lane PHY. > > > > Wouldn't the PCIe6a also have to switch to gen4x2 compatible on a board > > where PCIe6b is used? > > Nope, it stays the same (e.g. as the hardware block is the same). > > > > Perhaps you can rephrase this so that it doesn't sound like you are > > > using compatibles to configure PCIe6a? > > > > But currently we do configure PCIe6a based on compatibles. > > > > What am I missing ? > > No, as we've discussed in multiple threads already: > > https://lore.kernel.org/all/ZwPDxd9JJbgDeJTi@hovoldconsulting.com/ > https://lore.kernel.org/lkml/ZtG2dUVkdwBpBbix@hovoldconsulting.com/ > > Johan
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index dcf4fa55fbba58e162e5c7bebd40170342039172..b5bb665503c86c79940031bcb58a36a833918a4e 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -201,6 +201,7 @@ allOf: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy then: properties: resets:
The PCIe 6a PHY on X1E80100 uses both resets in 4-lanes mode as well. So fix the resets entries for it by adding the Gen4 4-lanes compatible alongside the 2-lanes one. Fixes: 0c5f4d23f776 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202410182029.n2zPkuGx-lkp@intel.com/ Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 1 + 1 file changed, 1 insertion(+) --- base-commit: d61a00525464bfc5fe92c6ad713350988e492b88 change-id: 20241018-phy-qcom-qmp-pcie-fix-x1e80100-gen4x4-resets-f1b41b935750 Best regards,