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Add the MIPI-LVDS combo subsystems. Signed-off-by: Liu Ying --- v4: * No change. v3: * No change. v2: * New patch. (Francesco) .../boot/dts/freescale/imx8qxp-ss-dc.dtsi | 4 + .../dts/freescale/imx8qxp-ss-mipi-lvds.dtsi | 437 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 3 + 3 files changed, 444 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi index 299720d8c99e..94c46a20597c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi @@ -152,10 +152,12 @@ port@1 { dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 { reg = <0>; + remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>; }; dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 { reg = <1>; + remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>; }; }; @@ -207,10 +209,12 @@ port@1 { dc0_pixel_link1_mipi_lvds_1_pxl2dpi: endpoint@0 { reg = <0>; + remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link1>; }; dc0_pixel_link1_mipi_lvds_0_pxl2dpi: endpoint@1 { reg = <1>; + remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link1>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi new file mode 100644 index 000000000000..fa7e7c33518e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include +#include + +/ { + mipi_lvds_0_ipg_clk: clock-mipi-lvds0-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "mipi_lvds_0_ipg_clk"; + }; + + mipi_lvds_1_ipg_clk: clock-mipi-lvds1-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "mipi_lvds_1_ipg_clk"; + }; +}; + +&dc0_pl_msi_bus { + mipi_lvds_0_irqsteer: interrupt-controller@56220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56220000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&mipi_lvds_0_lis_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + }; + + mipi_lvds_0_csr: syscon@56221000 { + compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd"; + reg = <0x56221000 0x1000>; + clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + + mipi_lvds_0_pxl2dpi: pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + fsl,sc-resource = ; + power-domains = <&pd IMX_SC_R_MIPI_0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>; + status = "disabled"; + }; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>; + status = "disabled"; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; + status = "disabled"; + }; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; + status = "disabled"; + }; + }; + }; + }; + + mipi_lvds_0_ldb: ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_0>; + status = "disabled"; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; + }; + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; + }; + }; + }; + }; + }; + + mipi_lvds_0_lis_lpcg: clock-controller@56223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_lvds_0_ipg_clk>; + clock-indices = ; + clock-output-names = "mipi_lvds_0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi_lvds_0_di_mipi_lvds_regs_lpcg: clock-controller@56223004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223004 0x4>; + #clock-cells = <1>; + clocks = <&mipi_lvds_0_ipg_clk>; + clock-indices = ; + clock-output-names = "mipi_lvds_0_di_mipi_lvds_regs_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi_lvds_0_pwm_lpcg: clock-controller@5622300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_lvds_0_ipg_clk>, + <&mipi_lvds_0_ipg_clk>; + clock-indices = , + , + ; + clock-output-names = "mipi_lvds_0_pwm_lpcg_clk", + "mipi_lvds_0_pwm_lpcg_ipg_clk", + "mipi_lvds_0_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + }; + + mipi_lvds_0_i2c0_lpcg: clock-controller@56223010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_lvds_0_ipg_clk>; + clock-indices = , + ; + clock-output-names = "mipi_lvds_0_i2c0_lpcg_clk", + "mipi_lvds_0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi_lvds_0_pwm: pwm@56224000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x56224000 0x1000>; + interrupt-parent = <&mipi_lvds_0_irqsteer>; + interrupts = <12>; + clocks = <&mipi_lvds_0_pwm_lpcg IMX_LPCG_CLK_4>, + <&mipi_lvds_0_pwm_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <3>; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + status = "disabled"; + }; + + mipi_lvds_0_i2c0: i2c@56226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56226000 0x1000>; + interrupt-parent = <&mipi_lvds_0_irqsteer>; + interrupts = <8>; + clocks = <&mipi_lvds_0_i2c0_lpcg IMX_LPCG_CLK_0>, + <&mipi_lvds_0_i2c0_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + status = "disabled"; + }; + + mipi_lvds_0_phy: phy@56228300 { + compatible = "fsl,imx8qxp-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + #phy-cells = <0>; + fsl,syscon = <&mipi_lvds_0_csr>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + status = "disabled"; + }; + + mipi_lvds_1_irqsteer: interrupt-controller@56240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56240000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&mipi_lvds_1_lis_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + }; + + mipi_lvds_1_csr: syscon@56241000 { + compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd"; + reg = <0x56241000 0x1000>; + clocks = <&mipi_lvds_1_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + + mipi_lvds_1_pxl2dpi: pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + fsl,sc-resource = ; + power-domains = <&pd IMX_SC_R_MIPI_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_1_pxl2dpi_dc0_pixel_link1: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc0_pixel_link1_mipi_lvds_1_pxl2dpi>; + status = "disabled"; + }; + + mipi_lvds_1_pxl2dpi_dc0_pixel_link0: endpoint@1 { + reg = <1>; + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_1_pxl2dpi>; + status = "disabled"; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_1_ldb_ch0_mipi_lvds_1_pxl2dpi>; + status = "disabled"; + }; + + mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_1_ldb_ch1_mipi_lvds_1_pxl2dpi>; + status = "disabled"; + }; + }; + }; + }; + + mipi_lvds_1_ldb: ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_1>; + status = "disabled"; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_1_phy>; + phy-names = "lvds_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_lvds_1_ldb_ch0_mipi_lvds_1_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch0>; + }; + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&mipi_lvds_1_phy>; + phy-names = "lvds_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_lvds_1_ldb_ch1_mipi_lvds_1_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch1>; + }; + }; + }; + }; + }; + + mipi_lvds_1_lis_lpcg: clock-controller@56243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_lvds_1_ipg_clk>; + clock-indices = ; + clock-output-names = "mipi_lvds_1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi_lvds_1_di_mipi_lvds_regs_lpcg: clock-controller@56243004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243004 0x4>; + #clock-cells = <1>; + clocks = <&mipi_lvds_1_ipg_clk>; + clock-indices = ; + clock-output-names = "mipi_lvds_1_di_mipi_lvds_regs_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi_lvds_1_pwm_lpcg: clock-controller@5624300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5624300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_lvds_1_ipg_clk>, + <&mipi_lvds_1_ipg_clk>; + clock-indices = , + , + ; + clock-output-names = "mipi_lvds_1_pwm_lpcg_clk", + "mipi_lvds_1_pwm_lpcg_ipg_clk", + "mipi_lvds_1_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + }; + + mipi_lvds_1_i2c0_lpcg: clock-controller@56243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_lvds_1_ipg_clk>; + clock-indices = , + ; + clock-output-names = "mipi_lvds_1_i2c0_lpcg_clk", + "mipi_lvds_1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + mipi_lvds_1_pwm: pwm@56244000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x56244000 0x1000>; + interrupt-parent = <&mipi_lvds_1_irqsteer>; + interrupts = <12>; + clocks = <&mipi_lvds_1_pwm_lpcg IMX_LPCG_CLK_4>, + <&mipi_lvds_1_pwm_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <3>; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + status = "disabled"; + }; + + mipi_lvds_1_i2c0: i2c@56246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56246000 0x1000>; + interrupt-parent = <&mipi_lvds_1_irqsteer>; + interrupts = <8>; + clocks = <&mipi_lvds_1_i2c0_lpcg IMX_LPCG_CLK_0>, + <&mipi_lvds_1_i2c0_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + status = "disabled"; + }; + + mipi_lvds_1_phy: phy@56248300 { + compatible = "fsl,imx8qxp-mipi-dphy"; + reg = <0x56248300 0x100>; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_PHY>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + #phy-cells = <0>; + fsl,syscon = <&mipi_lvds_1_csr>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 35cc82cbbcd1..25adc1090dec 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -55,6 +55,8 @@ aliases { i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; + mipi-dphy0 = &mipi_lvds_0_phy; + mipi-dphy1 = &mipi_lvds_1_phy; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; @@ -355,6 +357,7 @@ map0 { #include "imx8qxp-ss-img.dtsi" #include "imx8qxp-ss-vpu.dtsi" #include "imx8qxp-ss-dc.dtsi" +#include "imx8qxp-ss-mipi-lvds.dtsi" #include "imx8qxp-ss-adma.dtsi" #include "imx8qxp-ss-conn.dtsi" #include "imx8qxp-ss-lsio.dtsi"