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Thu, 20 Feb 2025 09:43:14 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 20 Feb 2025 01:43:08 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , CC: Krzysztof Kozlowski Subject: [PATCH v11 1/7] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy Date: Thu, 20 Feb 2025 15:12:45 +0530 Message-ID: <20250220094251.230936-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250220094251.230936-1-quic_varada@quicinc.com> References: <20250220094251.230936-1-quic_varada@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Mqw34Q5l79gzvj59udn6eXncnS03_a3x X-Proofpoint-ORIG-GUID: Mqw34Q5l79gzvj59udn6eXncnS03_a3x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-20_04,2025-02-20_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 phishscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502200071 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250220_014322_636862_1BA584D5 X-CRM114-Status: GOOD ( 15.48 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: Nitheesh Sekar Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Nitheesh Sekar Signed-off-by: Varadarajan Narayanan --- v8: Add 'Reviewed-by: Krzysztof Kozlowski' v7: * Add data type definition to 'num-lanes' v6: * Fix num-lanes definition * Make it mandatory v5: * Drop '3x1' & '3x2' from compatible string * Use 'num-lanes' to differentiate instead of '3x1' or '3x2' in compatible string * Describe clocks and resets instead of just maxItems v4: Remove reset-names as the resets are not used individually Remove clock-output-names as its usage is removed from driver Fix order in the 'required' section v3: Fix compatible string to be similar to other phys and rename file accordingly Fix clocks minItems -> maxItems Change one of the maintainer from Sricharan to Varadarajan v2: Rename the file to match the compatible Drop 'driver' from title Dropped 'clock-names' Fixed 'reset-names' --- .../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml new file mode 100644 index 000000000000..e39168d55d23 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm UNIPHY PCIe 28LP PHY + +maintainers: + - Nitheesh Sekar + - Varadarajan Narayanan + +description: + PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC + +properties: + compatible: + enum: + - qcom,ipq5332-uniphy-pcie-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: pcie pipe clock + - description: pcie ahb clock + + resets: + items: + - description: phy reset + - description: ahb reset + - description: cfg reset + + "#phy-cells": + const: 0 + + "#clock-cells": + const: 0 + + num-lanes: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + +required: + - compatible + - reg + - clocks + - resets + - "#phy-cells" + - "#clock-cells" + - num-lanes + +additionalProperties: false + +examples: + - | + #include + + pcie0_phy: phy@4b0000 { + compatible = "qcom,ipq5332-uniphy-pcie-phy"; + reg = <0x004b0000 0x800>; + + clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + + resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; + + #clock-cells = <0>; + + #phy-cells = <0>; + + num-lanes = <1>; + };