| Message ID | 20250310-sm8750_ufs_master-v2-4-0dfdd6823161@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add UFS support for SM8750 | expand |
On Mon, Mar 10, 2025 at 02:12:32PM -0700, Melody Olvera wrote: > From: Nitin Rawat <quic_nitirawa@quicinc.com> > > Add UFS host controller and PHY nodes for SM8750 SoC. > > Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> > Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sm8750.dtsi | 106 +++++++++++++++++++++++++++++++++++ > 1 file changed, 106 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi > index 529e4e4e1d0ea9e99e89c12d072e27c45091f29e..72f69e717ce049bb0c524aa389d837ecd1459535 100644 > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi > @@ -13,6 +13,7 @@ > #include <dt-bindings/power/qcom,rpmhpd.h> > #include <dt-bindings/power/qcom-rpmpd.h> > #include <dt-bindings/soc/qcom,rpmh-rsc.h> > +#include <dt-bindings/gpio/gpio.h> Sort includes alphabetically. > > / { > interrupt-parent = <&intc>; > @@ -2675,6 +2676,111 @@ gic_its: msi-controller@16040000 { > }; > }; > > + ufs_mem_phy: phy@1d80000 { > + compatible = "qcom,sm8750-qmp-ufs-phy"; > + reg = <0 0x01d80000 0 0x2000>; Use 0x0 for consistency. > + > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, > + <&tcsrcc TCSR_UFS_CLKREF_EN>; Please align the clocks. > + > + clock-names = "ref", > + "ref_aux", > + "qref"; > + > + resets = <&ufs_mem_hc 0>; > + reset-names = "ufsphy"; > + > + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; Here too. > + > + ufs_mem_hc: ufs@1d84000 { > + compatible = "qcom,sm8750-ufshc", > + "qcom,ufshc", > + "jedec,ufs-2.0"; Compatibles can be ordered in the same line. > + reg = <0 0x01d84000 0 0x3000>; 0x0 > + > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_UFS_PHY_AHB_CLK>, > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > + <&rpmhcc RPMH_LN_BB_CLK3>, > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + clock-names = "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; > + > + operating-points-v2 = <&ufs_opp_table>; > + > + resets = <&gcc GCC_UFS_PHY_BCR>; > + reset-names = "rst"; > + > + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "ufs-ddr", > + "cpu-ufs"; > + > + power-domains = <&gcc GCC_UFS_PHY_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + > + iommus = <&apps_smmu 0x60 0>; > + dma-coherent; > + > + lanes-per-direction = <2>; > + > + phys = <&ufs_mem_phy>; > + phy-names = "ufsphy"; > + > + #reset-cells = <1>; > + > + status = "disabled"; > + Extra newline - Mani
On 3/17/2025 10:28 PM, Manivannan Sadhasivam wrote: > On Mon, Mar 10, 2025 at 02:12:32PM -0700, Melody Olvera wrote: >> From: Nitin Rawat <quic_nitirawa@quicinc.com> >> >> Add UFS host controller and PHY nodes for SM8750 SoC. >> >> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> >> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> >> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sm8750.dtsi | 106 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 106 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> index 529e4e4e1d0ea9e99e89c12d072e27c45091f29e..72f69e717ce049bb0c524aa389d837ecd1459535 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> @@ -13,6 +13,7 @@ >> #include <dt-bindings/power/qcom,rpmhpd.h> >> #include <dt-bindings/power/qcom-rpmpd.h> >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >> +#include <dt-bindings/gpio/gpio.h> > Sort includes alphabetically. Ack. > >> >> / { >> interrupt-parent = <&intc>; >> @@ -2675,6 +2676,111 @@ gic_its: msi-controller@16040000 { >> }; >> }; >> >> + ufs_mem_phy: phy@1d80000 { >> + compatible = "qcom,sm8750-qmp-ufs-phy"; >> + reg = <0 0x01d80000 0 0x2000>; > Use 0x0 for consistency. Ack. > >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, >> + <&tcsrcc TCSR_UFS_CLKREF_EN>; > Please align the clocks. Ack. > >> + >> + clock-names = "ref", >> + "ref_aux", >> + "qref"; >> + >> + resets = <&ufs_mem_hc 0>; >> + reset-names = "ufsphy"; >> + >> + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; > Here too. I'm assuming you mean the curly brace; ack. > >> + >> + ufs_mem_hc: ufs@1d84000 { >> + compatible = "qcom,sm8750-ufshc", >> + "qcom,ufshc", >> + "jedec,ufs-2.0"; > Compatibles can be ordered in the same line. Ack. > >> + reg = <0 0x01d84000 0 0x3000>; > 0x0 Ack. > >> + >> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_UFS_PHY_AHB_CLK>, >> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, >> + <&rpmhcc RPMH_LN_BB_CLK3>, >> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; >> + clock-names = "core_clk", >> + "bus_aggr_clk", >> + "iface_clk", >> + "core_clk_unipro", >> + "ref_clk", >> + "tx_lane0_sync_clk", >> + "rx_lane0_sync_clk", >> + "rx_lane1_sync_clk"; >> + >> + operating-points-v2 = <&ufs_opp_table>; >> + >> + resets = <&gcc GCC_UFS_PHY_BCR>; >> + reset-names = "rst"; >> + >> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; >> + interconnect-names = "ufs-ddr", >> + "cpu-ufs"; >> + >> + power-domains = <&gcc GCC_UFS_PHY_GDSC>; >> + required-opps = <&rpmhpd_opp_nom>; >> + >> + iommus = <&apps_smmu 0x60 0>; >> + dma-coherent; >> + >> + lanes-per-direction = <2>; >> + >> + phys = <&ufs_mem_phy>; >> + phy-names = "ufsphy"; >> + >> + #reset-cells = <1>; >> + >> + status = "disabled"; >> + > Extra newline Will remove. Thanks, Melody
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 529e4e4e1d0ea9e99e89c12d072e27c45091f29e..72f69e717ce049bb0c524aa389d837ecd1459535 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/gpio/gpio.h> / { interrupt-parent = <&intc>; @@ -2675,6 +2676,111 @@ gic_its: msi-controller@16040000 { }; }; + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,sm8750-qmp-ufs-phy"; + reg = <0 0x01d80000 0 0x2000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>; + + clock-names = "ref", + "ref_aux", + "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sm8750-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 = <&ufs_opp_table>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x60 0>; + dma-coherent; + + lanes-per-direction = <2>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-403000000 { + opp-hz = /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + apps_rsc: rsc@16500000 { compatible = "qcom,rpmh-rsc"; reg = <0x0 0x16500000 0x0 0x10000>,