From patchwork Fri Mar 21 12:14:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem X-Patchwork-Id: 14025332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49EABC36007 for ; Fri, 21 Mar 2025 12:14:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References: Message-Id:MIME-Version:Subject:Date:From:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tC10nDo9lkdpMfHyQVUeFkOY/2VEBpu0oRzMkyMLNaE=; b=BbulMvpKX/YAh+ 5Ltk2Dosp0k9mrV1YTTQnowZK303MnUODH265N75HXFbGH2ZMNosk6MWGF9aCzcuW2JNs4KfuX/DF QXHKvCWheN14eS11t3j8bGfEc8OtQnqgOHIWVNV9gHU9iTmRO9maPZlbuyLM0E5EOtiACWXFT61Vu weuQCsRykjO6Eb08odtNAQON3Itw0rqlhijJKkjLARmeu3gBxfHlElKocWll4Ij4V54jVDohsavNu Yy+SxjITSR5+mfRGIenzjYLVsuxlF0kK2mBnc5TN8PhElLUW5SbtPUz3Ekvlcvzd1rxmpK62+TyzG zi5P1UEFBpmX9cPI2gwA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tvbH0-0000000Ejit-0F2H; Fri, 21 Mar 2025 12:14:50 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tvbGx-0000000Ejgs-34uA for linux-phy@lists.infradead.org; Fri, 21 Mar 2025 12:14:47 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 65DB7615D6; Fri, 21 Mar 2025 12:14:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id F0E10C4CEEF; Fri, 21 Mar 2025 12:14:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742559286; bh=g1aNlT6mR+0lzBikCDDy3QE+nBuvGIYwMOVapKIIDCU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Dr5Q2lQwM0Yn0le6dcbWEz73T7tcLk907yOdC8n3T2sxy+TnmEC5Y2AgJMMm9lNa/ Ym4rl8l5cEBhtpoQmDnxTv/8epxQPXLGMy3EONhUZD2vRIEaWLuv4yq3y3jFo9Bklc 6ZxgXMUm4gfKBozNSd1EUE1CZKbT/yeO95izh1cq56+OW3NJQyJaunrWMZMGui7+iT HmcUrMKjkqtd7pExy2/SppdLywWLKvVJO1B57ZSbtmHr/b7f4mV0yhDZTX9PN55UPE 8HY2olzBPIvqA94klD4Zaxzd5VXWndBkbEF/fatCBrnuUEQ0Ocm3PdXTHAXCKE5caA YmUErXMXvkx0Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E58CCC36007; Fri, 21 Mar 2025 12:14:45 +0000 (UTC) Date: Fri, 21 Mar 2025 16:14:40 +0400 Subject: [PATCH v6 2/6] phy: qualcomm: qcom-uniphy-pcie 28LP add support for IPQ5018 MIME-Version: 1.0 Message-Id: <20250321-ipq5018-pcie-v6-2-b7d659a76205@outlook.com> References: <20250321-ipq5018-pcie-v6-0-b7d659a76205@outlook.com> In-Reply-To: <20250321-ipq5018-pcie-v6-0-b7d659a76205@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nitheesh Sekar , Varadarajan Narayanan , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, George Moussalem , 20250317100029.881286-2-quic_varada@quicinc.com, Sricharan Ramabadhran X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1742559282; l=2412; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=J/nwlaH52lH5Y8C/GSWQOuJkQODLSqbcJAs7EDLQiiU=; b=6YgoV6IU2BviKAIuZronVq4XXd/UPdZN/tAlWig/d2rvBUMW5uCbEdcpJ/5JsZSZ/m4blnqVo ZVEk3BGDHqNBfRAS+aXTasmspVPQdsmq/zo+N8mGIix66q4MN7xN6ty X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: george.moussalem@outlook.com Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: George Moussalem From: Nitheesh Sekar The Qualcomm UNIPHY PCIe PHY 28LP is found on both IPQ5332 and IPQ5018. Adding the PHY init sequence, pipe clock rate, and compatible for IPQ5018. Signed-off-by: Nitheesh Sekar Signed-off-by: Sricharan Ramabadhran Signed-off-by: George Moussalem Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 45 ++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c index c8b2a3818880..324c0a5d658e 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c @@ -75,6 +75,40 @@ struct qcom_uniphy_pcie { #define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy) +static const struct qcom_uniphy_pcie_regs ipq5018_regs[] = { + { + .offset = SSCG_CTRL_REG_4, + .val = 0x1cb9, + }, { + .offset = SSCG_CTRL_REG_5, + .val = 0x023a, + }, { + .offset = SSCG_CTRL_REG_3, + .val = 0xd360, + }, { + .offset = SSCG_CTRL_REG_1, + .val = 0x1, + }, { + .offset = SSCG_CTRL_REG_2, + .val = 0xeb, + }, { + .offset = CDR_CTRL_REG_4, + .val = 0x3f9, + }, { + .offset = CDR_CTRL_REG_5, + .val = 0x1c9, + }, { + .offset = CDR_CTRL_REG_2, + .val = 0x419, + }, { + .offset = CDR_CTRL_REG_1, + .val = 0x200, + }, { + .offset = PCS_INTERNAL_CONTROL_2, + .val = 0xf101, + }, +}; + static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = { { .offset = PHY_CFG_PLLCFG, @@ -88,6 +122,14 @@ static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = { }, }; +static const struct qcom_uniphy_pcie_data ipq5018_data = { + .lane_offset = 0x800, + .phy_type = PHY_TYPE_PCIE_GEN2, + .init_seq = ipq5018_regs, + .init_seq_num = ARRAY_SIZE(ipq5018_regs), + .pipe_clk_rate = 125 * MEGA, +}; + static const struct qcom_uniphy_pcie_data ipq5332_data = { .lane_offset = 0x800, .phy_type = PHY_TYPE_PCIE_GEN3, @@ -212,6 +254,9 @@ static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int id) static const struct of_device_id qcom_uniphy_pcie_id_table[] = { { + .compatible = "qcom,ipq5018-uniphy-pcie-phy", + .data = &ipq5018_data, + }, { .compatible = "qcom,ipq5332-uniphy-pcie-phy", .data = &ipq5332_data, }, {