From patchwork Fri Mar 21 12:14:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem X-Patchwork-Id: 14025335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22F31C36009 for ; Fri, 21 Mar 2025 12:14:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References: Message-Id:MIME-Version:Subject:Date:From:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tNrtiG4A/DWZgY4JDo1XL2gWAHkRwZAQHLjZQp4L15I=; b=SFZtPOhX8vS9xI uXuJEGtIeWGH/OGO0RYwHWZsgdhNt+LUZHgpbNZTTuRUna0gqEy0+/vRn2J9o9yMnoxvQTq0tcNML kT+tfOH4YLUxxsf/x/QDfGXkS+uqDmgJjtp2wSGGf1yyR23UBqTvucNcf/MFJ7xJor1mgz/loYuLW trFguXzFcKojWN51dHweDodks8IFpLsvrqNKtzZyWFui2M5ZBSEBJzzgIFXF5qixFKzdclRGVoRD7 H5PMLAatywcb5UsN3WEsZAguPqujLnwKVjulj9f4yqVOle/Tc1cl0BqtPqRneZmYWIzIe3JrYZOsF 8k0YGkM1+zih/5A3/6YQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tvbH0-0000000EjkC-3hx5; Fri, 21 Mar 2025 12:14:50 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tvbGx-0000000Ejgj-1UIr for linux-phy@lists.infradead.org; Fri, 21 Mar 2025 12:14:48 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id B48415C6BCE; Fri, 21 Mar 2025 12:12:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id 429A4C116C6; Fri, 21 Mar 2025 12:14:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742559286; bh=FkOn0IjuH79qFq1TeqcZzJ6FLwLXQqmZ+ZrnVIsRnKw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XHZji32LBz6Rfv9VnfXn8iHOhd+Fj6X9UnKabb5mAya1UjqQLotZp0E9KUzADNXvU eqebxjFl24Xzy/XtdeXfSeYTNROKzWsggBn/QOEx+4yDltogyHnL4j0OVX2Sg9+u/W tM6LKpKpyQm52FqGoIKpiYyYDzvy8dVKEFnrzvl+u4Gdmi/veQzJBBZiU93zxuw2Qt d89rCC3TesTM2ExDNMp+S3sNBwgln0FH7i+LyUU2iQzZp4278ySLcjM5kNEY7KlF9L WixyuMCme3U/cXpoB2JMlRN5CgWTfSsZWFAjTPvzHpnG/CxBimKoMOWDs6jOyloi5p h/iJR3PFVpY5w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38886C36007; Fri, 21 Mar 2025 12:14:46 +0000 (UTC) Date: Fri, 21 Mar 2025 16:14:43 +0400 Subject: [PATCH v6 5/6] arm64: dts: qcom: ipq5018: Add PCIe related nodes MIME-Version: 1.0 Message-Id: <20250321-ipq5018-pcie-v6-5-b7d659a76205@outlook.com> References: <20250321-ipq5018-pcie-v6-0-b7d659a76205@outlook.com> In-Reply-To: <20250321-ipq5018-pcie-v6-0-b7d659a76205@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nitheesh Sekar , Varadarajan Narayanan , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, George Moussalem , 20250317100029.881286-2-quic_varada@quicinc.com, Sricharan R X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1742559282; l=7376; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=WAeuLjqK9NUk+ZyBqC1MGZazKF8I8F2kraQ/dHrYTKM=; b=IY6TGNJgxP9BMtehig95sqAbfVWK5nJJYpogmmusqVWNxG/3fWI8ng05g553So6vRA+JoHFHS +IJj9pvKJTODGLiRjph5ncpaoGO3lCPdZAjjWtI/W6x8zH9TSfjqDv5 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250321_051447_471122_89A97A38 X-CRM114-Status: UNSURE ( 8.54 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: george.moussalem@outlook.com Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: George Moussalem From: Nitheesh Sekar Add phy and controller nodes for a 2-lane Gen2 and a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and one global interrupt. Signed-off-by: Nitheesh Sekar Signed-off-by: Sricharan R Signed-off-by: George Moussalem Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 234 +++++++++++++++++++++++++++++++++- 1 file changed, 232 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 8914f2ef0bc4..d08034b57e80 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -147,6 +147,40 @@ usbphy0: phy@5b000 { status = "disabled"; }; + pcie1_phy: phy@7e000{ + compatible = "qcom,ipq5018-uniphy-pcie-phy"; + reg = <0x0007e000 0x800>; + + clocks = <&gcc GCC_PCIE1_PIPE_CLK>; + + resets = <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + + #clock-cells = <0>; + #phy-cells = <0>; + + num-lanes = <1>; + + status = "disabled"; + }; + + pcie0_phy: phy@86000{ + compatible = "qcom,ipq5018-uniphy-pcie-phy"; + reg = <0x00086000 0x800>; + + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + + #clock-cells = <0>; + #phy-cells = <0>; + + num-lanes = <2>; + + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; @@ -170,8 +204,8 @@ gcc: clock-controller@1800000 { reg = <0x01800000 0x80000>; clocks = <&xo_board_clk>, <&sleep_clk>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>, <0>, @@ -387,6 +421,202 @@ frame@b128000 { status = "disabled"; }; }; + + pcie1: pcie@80000000 { + compatible = "qcom,pcie-ipq5018"; + reg = <0x80000000 0xf1d>, + <0x80000f20 0xa8>, + <0x80001000 0x1000>, + <0x00078000 0x3000>, + <0x80100000 0x1000>, + <0x0007b000 0x1000>; + reg-names = "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + max-link-speed = <2>; + #address-cells = <3>; + #size-cells = <2>; + + phys = <&pcie1_phy>; + phy-names ="pciephy"; + + ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>, + <0x02000000 0 0x80300000 0x80300000 0 0x10000000>; + + msi-map = <0x0 &v2m0 0x0 0xff8>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, + <&gcc GCC_PCIE1_AXI_M_CLK>, + <&gcc GCC_PCIE1_AXI_S_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; + clock-names = "iface", + "axi_m", + "axi_s", + "ahb", + "aux", + "axi_bridge"; + + resets = <&gcc GCC_PCIE1_PIPE_ARES>, + <&gcc GCC_PCIE1_SLEEP_ARES>, + <&gcc GCC_PCIE1_CORE_STICKY_ARES>, + <&gcc GCC_PCIE1_AXI_MASTER_ARES>, + <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE1_AHB_ARES>, + <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", + "axi_m_sticky", + "axi_s_sticky"; + + status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie0: pcie@a0000000 { + compatible = "qcom,pcie-ipq5018"; + reg = <0xa0000000 0xf1d>, + <0xa0000f20 0xa8>, + <0xa0001000 0x1000>, + <0x00080000 0x3000>, + <0xa0100000 0x1000>, + <0x00083000 0x1000>; + reg-names = "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + max-link-speed = <2>; + #address-cells = <3>; + #size-cells = <2>; + + phys = <&pcie0_phy>; + phy-names ="pciephy"; + + ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>, + <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>; + + msi-map = <0x0 &v2m0 0x0 0xff8>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, + <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>; + clock-names = "iface", + "axi_m", + "axi_s", + "ahb", + "aux", + "axi_bridge"; + + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_SLEEP_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", + "axi_m_sticky", + "axi_s_sticky"; + + status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; }; timer {