| Message ID | 20250321-ipq5018-pcie-v6-6-b7d659a76205@outlook.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable IPQ5018 PCI support | expand |
On Fri, Mar 21, 2025 at 04:14:44PM +0400, George Moussalem via B4 Relay wrote: > From: Nitheesh Sekar <quic_nsekar@quicinc.com> > > Enable the PCIe controller and PHY nodes for RDP 432-c2. > > Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > Signed-off-by: George Moussalem <george.moussalem@outlook.com> > --- > arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 40 ++++++++++++++++++++++++++ > 1 file changed, 40 insertions(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Minor question below. > + > +&pcie0_phy { > + status = "okay"; If you have schematics, are you sure that there are no supplies for the PCIe PHY / PCIe PLLs on this board? > +}; > + > &sdhc_1 { > pinctrl-0 = <&sdc_default_state>; > pinctrl-names = "default";
On Fri, Mar 21, 2025 at 04:14:44PM +0400, George Moussalem via B4 Relay wrote: > From: Nitheesh Sekar <quic_nsekar@quicinc.com> > > Enable the PCIe controller and PHY nodes for RDP 432-c2. > > Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > Signed-off-by: George Moussalem <george.moussalem@outlook.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 40 ++++++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts > index 8460b538eb6a..43def95e9275 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts > +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts > @@ -9,6 +9,8 @@ > > #include "ipq5018.dtsi" > > +#include <dt-bindings/gpio/gpio.h> > + > / { > model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2"; > compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018"; > @@ -28,6 +30,20 @@ &blsp1_uart1 { > status = "okay"; > }; > > +&pcie0 { > + pinctrl-0 = <&pcie0_default>; > + pinctrl-names = "default"; > + > + perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>; > + > + status = "okay"; > +}; > + > +&pcie0_phy { > + status = "okay"; > +}; > + > &sdhc_1 { > pinctrl-0 = <&sdc_default_state>; > pinctrl-names = "default"; > @@ -43,6 +59,30 @@ &sleep_clk { > }; > > &tlmm { > + pcie0_default: pcie0-default-state { > + clkreq-n-pins { > + pins = "gpio14"; > + function = "pcie0_clk"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + > + perst-n-pins { > + pins = "gpio15"; > + function = "gpio"; > + drive-strength = <8>; > + bias-pull-up; > + output-low; > + }; > + > + wake-n-pins { > + pins = "gpio16"; > + function = "pcie0_wake"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > + > sdc_default_state: sdc-default-state { > clk-pins { > pins = "gpio9"; > > -- > 2.48.1 > >
On 3/21/25 18:13, Dmitry Baryshkov wrote: > On Fri, Mar 21, 2025 at 04:14:44PM +0400, George Moussalem via B4 Relay wrote: >> From: Nitheesh Sekar <quic_nsekar@quicinc.com> >> >> Enable the PCIe controller and PHY nodes for RDP 432-c2. >> >> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >> Signed-off-by: George Moussalem <george.moussalem@outlook.com> >> --- >> arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 40 ++++++++++++++++++++++++++ >> 1 file changed, 40 insertions(+) > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > > Minor question below. > >> + >> +&pcie0_phy { >> + status = "okay"; > > If you have schematics, are you sure that there are no supplies for the > PCIe PHY / PCIe PLLs on this board? I don't have the schematics, but none of the boards I've personally tested (mostly Linksys devices) require any supply. I've also checked the downstream board files documented on codelinaro for ipq5018, and none mention a supply. > >> +}; >> + >> &sdhc_1 { >> pinctrl-0 = <&sdc_default_state>; >> pinctrl-names = "default"; > Best regards, George
On 3/24/25 9:06 AM, George Moussalem wrote: > > > On 3/21/25 18:13, Dmitry Baryshkov wrote: >> On Fri, Mar 21, 2025 at 04:14:44PM +0400, George Moussalem via B4 Relay wrote: >>> From: Nitheesh Sekar <quic_nsekar@quicinc.com> >>> >>> Enable the PCIe controller and PHY nodes for RDP 432-c2. >>> >>> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> >>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >>> Signed-off-by: George Moussalem <george.moussalem@outlook.com> >>> --- >>> arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 40 ++++++++++++++++++++++++++ >>> 1 file changed, 40 insertions(+) >> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> >> >> Minor question below. >> >>> + >>> +&pcie0_phy { >>> + status = "okay"; >> >> If you have schematics, are you sure that there are no supplies for the >> PCIe PHY / PCIe PLLs on this board? > > I don't have the schematics, but none of the boards I've personally tested (mostly Linksys devices) require any supply. I've also checked the downstream board files documented on codelinaro for ipq5018, and none mention a supply. It looks like on the reference board it's connected to an essentially always-on supply, I'd expect that to be the case on yours as well Konrad
On 3/21/25 1:14 PM, George Moussalem via B4 Relay wrote: > From: Nitheesh Sekar <quic_nsekar@quicinc.com> > > Enable the PCIe controller and PHY nodes for RDP 432-c2. > > Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > Signed-off-by: George Moussalem <george.moussalem@outlook.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts index 8460b538eb6a..43def95e9275 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -9,6 +9,8 @@ #include "ipq5018.dtsi" +#include <dt-bindings/gpio/gpio.h> + / { model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2"; compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018"; @@ -28,6 +30,20 @@ &blsp1_uart1 { status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; +}; + &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; @@ -43,6 +59,30 @@ &sleep_clk { }; &tlmm { + pcie0_default: pcie0-default-state { + clkreq-n-pins { + pins = "gpio14"; + function = "pcie0_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio15"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio16"; + function = "pcie0_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio9";